HFIXF1110CC Intel, HFIXF1110CC Datasheet - Page 79

• Manufacturer Part Number: HFIXF1110CC
• Manufacturer: Intel

Specifications of HFIXF1110CC

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

5.4.4.2
5.4.4.3
5.4.4.4
Datasheet
Note: Only one optical module I
carried out to the I
the first Write is lost. To ensure no data is lost, make sure Write complete = 1 before starting the
next Write sequence.
I
This section describes the I
an internal state machine. Specific protocol states are defined below, with an additional description
of the hardware pins used on the interface.
The Serial Clock Line (I
clock and is driven off the rising edge by the IXF1110 and off the falling edge by the optical
module. The IXF1110 has only one I
I
The Serial Data (I
are open drain.
Port Protocol Operation
Clock and Data Transitions
The I
only during the I
periods indicate a start or stop condition.
2
2
2. When this register is written and the I
3. The state machine uses the data in the Device ID and Register Address fields to build the data
4. The I
5. The I
6. The data is written through the CPU interface. The CPU must poll the Write_Complete bit
C_CLK runs continuously when enabled (I
C Protocol Specifics
examines the Port Address Select and enables the I
frame to be sent to the optical module.
actual data between the IXF1110 and the selected optical module (refer to the details in
Section 5.4.4.2, “I
bits [23:16] of the I
Register to ‘1’ to signify that the Write Access is complete.
until it is set to ‘1. Only once this bit is set, it is safe to request a new access.
2
C_DATA is normally pulled High with an extra device. Data on the I
2
2
C DATA_WRITE_FSM internal state machine takes over the task of transferring the
C DATA_WRITE_FSM internal state machine uses the data from the Write_Data field,
Intel
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
2
C_CLK Low time periods (see
2
2
C_DATA_0:9) pins (one per port) are bi-directional for serial data transfer, and
C Control Register before a result is returned for the previous Write, the data for
2
C Protocol Specifics” on page
2
Order Number: 250210, Revision: 009
C Data Register, and sets the Write_Complete bit, bit 22 of the I
2
C_CLK) is an IXF1110 output. The serial data is synchronous with this
2
C access sequence can be run at any given time. If a second Write is
2
C protocol behavior supported by the IXF1110, which is controlled by
Intel
2
C_CLK line that drives all of the optical modules. The
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
2
C Start bit is at a Logic 1, the I
2
C Enable = 01h0).
Figure
79).
2
16). Data changes during I
C_DATA_0:9 output for the selected port.
2
C access state machine
2
C_DATA pin changes
2
C_CLK High
2
07-Oct-2005
C Control
79