IDT77V1254L25PGI IDT, Integrated Device Technology Inc, IDT77V1254L25PGI Datasheet - Page 35

• Manufacturer Part Number: IDT77V1254L25PGI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1254L25PGI

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 4
• Type Of Atm Phy Interface: DPI/UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 144
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Master Control Registers
Interrupt Status Registers
Diagnostic Control Registers
Addresses: 0x00, 0x10, 0x20, 0x30
7
6
5
4
3
2
1
0
Addresses: 0x01, 0x11, 0x21, 0x31
7
6
5
4
3
2
1
0
Addresses: 0x02, 0x12, 0x22, 0x32
7
IDT77V1254L25
Bit
Bit
Bit
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
sticky
sticky
sticky
sticky
sticky
sticky
R/W
Type
Type
Type
0
1 = discard errored cells Discard Receive Error Cells - On receipt of any cell with an error (e.g. short cell, invalid command mnemonic, receive
0 = all interrupts
0 = disabled
1 = discard idle cells
0 = not halted
0 = cell mode
1 = enable interrupts
Reserved
0 = Bad Signal
0
0
0
0
0
0
0 = normal
Initial State
Initial State
Initial State
Reserved
HEC error (if enabled), this cell will be discarded and will not enter the receive FIFO.
Enable Cell Error Interrupts Only - If Bit 0 in this register is set (Interrupts Enabled), setting of this bit enables only
"Received Cell Error" (as defined in bit 6) to trigger interrupt line.
Transmit Data Parity Check - Directs TC to check parity of TXDATA against parity bit located in TXPARITY.
Discard Received Idle Cells - Directs TC to discard received idle (VPI/VCI = 0) cells from PMD without signalling
external systems.
Halt Transmit - Halts transmission of data from TC to PMD and forces the TXD outputs to the "0" state
UTOPIA Level 1 mode select: - 0 = cell mode, 1 = byte mode. Not applicable for Utopia 2 or DPI modes.
Enable Interrupt Pin (Interrupt Mask Bit) - Enables interrupt output pin (pin 85). If cleared, pin is always high and
interrupt is masked. If set, an interrupt will be signaled by setting the interrupt pin to "0". It doesn’t affect the Interrupt
Status Registers.
Good Signal Bit - See definition on page 13.
1 - Good Signal
0 - Bad Signal
HEC error cell received - Set when a HEC error is detected on received cell.
"Short Cell" Received - Interrupt signal which flags received cells with fewer than 53 bytes. This condition is detected
when receiving Start-of-Cell command bytes with fewer than 53 bytes between them.
Transmit Parity Error - If Bit 4 of Register 0x00 / 0x10 / 0x20 / 0x30 is set (Transmit Data Parity Check), this interrupt
flags a transmit data parity error condition. Odd parity is used.
Receive Signal Condition change - This interrupt is set when the received ’signal’ changes either from ’bad to good’
or from ’good to bad’.
Received Symbol Error - Set when an undefined 5-bit symbol is received.
Receive FIFO Overflow - Interrupt which indicates when the receive FIFO has filled and cannot accept additional data.
Force TXCLAV deassert - (applicable only in Utopia 1 and 2 modes) Used during line loopback mode to prevent
upstream system from continuing to send data to the 77V1254L25.
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Function
Function
Function
December 2004