IDT77V1054L25PF IDT, Integrated Device Technology Inc, IDT77V1054L25PF Datasheet - Page 14

• Manufacturer Part Number: IDT77V1054L25PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1054L25PF

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Package Type: TQFP
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

UTILITY BUS
registers within the IDT77V1054. These registers are used to select
desired operating characteristics and functions, and to communicate
status to external systems.
data bus (AD[7:0]) where the register address is latched via the
Address Latch Enable (ALE) signal.
The Utility Bus interface is comprised of the following pins:
Read Operation
register read is performed as follows:
Write Operation
INTERRUPT OPERATIONS
and signalling conditions which are useful both during ‘normal’ opera-
tion, and as diagnostic aids. Refer to the Status and Control Register
List section.
Registers. When this bit is cleared (set to 0), interrupt signalling is
prevented on the respective port. The Interrupt Mask Registers allow
IDT77V1054
Quad Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2
1. Initial condition:
2. Set up register address:
3. Read register data:
1. Initial condition:
2. Set up register address:
3. Write data:
The Utility Bus is a byte-wide interface that provides access to the
The Utility Bus is implemented using a multiplexed address and
Refer to the Utility Bus timing waveforms in Figures 18 - 19. A
A register write is performed as described below:
The IDT77V1054 provides a variety of selectable interrupt
Overall interrupt control is provided via bit 0 of the Master Control
(according to timing specification); reset WR
to logic 1 to complete register write cycle.
- RD, WR, CS not asserted (logic 1)
- ALE not asserted (logic 0)
- place desired register address on AD[7:0]
- set ALE to logic 1;
- latch this address by setting ALE to logic 0.
- Remove register address data from AD[7:0]
- assert CS by setting to logic 0;
- assert RD by setting to logic 0
- wait minimum pulse width time (see AC specifications)
- RD, WR, CS not asserted (logic 1)
- ALE not asserted (logic 0)
- place desired register address on AD[7:0]
- set ALE to logic 1;
- latch this address by setting ALE to logic 0.
- place data on AD[7:0]
- assert CS by setting to logic 0;
- assert WR (logic 0) for minimum time
AD[7:0], ALE, CS, RD, WR
14
individual masking of different interrupt sources. Additional interrupt
signal control is provided by bit 5 of the Master Control Registers.
When this bit is set (=1), receive cell errors will be flagged via interrupt
signalling and all other interrupt conditions are masked. These errors
include:
clearing bit 5 in the Master Control Registers. INT (pin 108) will go to
a low state when an interrupt condition is detected. The external
system should then interrogate the 77V1054 to determine which one
(or more) conditions caused this flag, and reset the interrupt for further
occurrences. This is accomplished by reading the Interrupt Status
Registers. Decoding the bits in these bytes will tell which error
condition caused the interrupt. Reading these registers also:
problems.
LED CONTROL AND SIGNALLING
mA. As an example, the RxLED outputs are described in the truth
table:
provide for a two-LED condition indicator. These could also be
different colors to provide simple status indication at a glance. (The
minimum value for R should be 330 ).
TxLED Truth Table
- Bad receive HEC
- Short (fewer than 53 bytes) cells
- Received cell symbol error
- clears the (sticky) interrupt status bits in the registers that are read
- resets INT
Normal interrupt operations are performed by setting bit 0 and
This leaves the interrupt system ready to signal an alarm for further
The LED outputs provide bi-directional LED drive capability of 8
As illustrated in the following drawing, this could be connected to
RxLED(3:0)
TxLED(3:0)
Cells not being transmitted
Cells not being received
Cells being transmitted
Cells being received
STATE
STATE
R
R
Figure 11.
3.3V
not being received or
(Indicates: Cells are
being received or
(Indicates: Cells
transmitted)
transmitted)
PIN VOLTAGE
PIN VOLTAGE
3505 drw 32
High
High
Low
Low
Preliminary
.
3505 tbl 10
3505 tbl 11