IDT77V107L25PFI IDT, Integrated Device Technology Inc, IDT77V107L25PFI Datasheet - Page 2

• Manufacturer Part Number: IDT77V107L25PFI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V107L25PFI

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 1
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

uniquely defined such that this bit sequence cannot be duplicated by
concatenating any two other valid symbols. The escape symbol is used
incombination with a second symbol to form command symbol pairs.
Two command symbol pairs are defined as start-of-cell indicators, and
one is used as the 8kHz timing marker.
valid symbols which are then transmitted across the line. When a
complete cell is available for transmission, the TC transmits the appro-
priate start-of-cell command symbol pair followed immediately the the
scrambled and encoded 53-byte cell. A falling edge on the TxREF pin
results in the insertion of an 8kHz timing marker in the transmit stream.
achieves symbol framing (as described below). Start-of-cell command
symbol pairs and 8kHz timing symbol pair are handled appropriately,
with receive cells being placed into the receive FIFO.
as a switch core or SAR) through an 8-bit Utopia Level 2 interface.
asynchronous read/write handshake, provides software access to
numerous internal control and status registers.
marker, and provide LED indication of receive and transmit status.
IDT77V107
In the absence of a cell to transmit, the TC will continue to generate
The receiver PMD performs clock and data recovery. The TC
On the cell side, the 77V107 connects to an ATM layer device (such
An 8-bit muxed address and data bus, controlled by a conventional
Additional pins permit insertion and extraction of an 8kHz timing
TXPARITY
TXADDR0
TXADDR1
TXADDR2
TXADDR3
TXADDR4
TXDATA0
TXDATA1
TXDATA2
TXDATA3
TXDATA4
TXDATA5
TXDATA6
TXDATA7
TXCLAV
RXREF
TXSOC
TXREF
TXLED
TXEN
GND
GND
VDD
VDD
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
100
26 27 28
99
98
29
97
Pin 1 Index
30 31 32 33 34
96
95
94
Figure 1 Pin Assignments
93
92
91
35 36 37
90
IDT77V107
2 of 24
89
88
38
87
39 40 41 42 43 44 45 46 47 48
Auto-Synchronization and Good
Signal Indication
allows it to achieve 4b5b symbol framing on any valid data stream. This
is an improvement on earlier products which could frame only on the
escape symbol, which occurs only in start-of-cell or 8kHz (X8) timing
marker symbol pairs.
the 77V107 receive section to achieve symbol framing and properly indi-
cate receive signal status, even in the absence of ATM cells or 8kHz
(X8) timing markers in the receive data stream. A state machine moni-
tors the received symbols and asserts the "Good Signal" status bit when
a valid signal is being received. "Good Signal" is deasserted and the
receive FIFO is disabled when the signal is lost. This is sometimes
referred to as Loss of Signal (LOS).
Operation at 51.2 Mbps
77V107 is also specified to operate at 51.2 Mbps. Except for the
doubled bit rate, all other aspects of operation are identical to the 25.6
Mbps mode. Other aspects of the ATM Forum Residential Broadband
standard (af-rbb-phy-0101.000) at 51.2 Mbps are not supported.
frequency (OSC pin) and a software control bit. OSC is 32 MHz for the
25.6 Mbps line rate, and either 32 or 64 MHz for the 51.2 Mbps line rate.
Mbps operation have a higher bandwidth than magnetics optimized for
25.6 Mbps.
86
85
The 77V107 features a new receiver synchronization algorithm that
ATM25 transceivers always transmit valid 4b5b symbols, allowing
In addition to operation at the standard rate of 25.6 Mbps, the
Rate selection is determined by a combination of the reference clock
See Figure 15 for recommended line magnetics. Magnetics for 51.2
84
83
82
81
80
79
78
77
49
76
50
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DA
NC
NC
NC
NC
NC
RCO
VDD
AD7
AD6
AD5
AD4
GND
AD3
AD2
AD1
AD0
ALE
CS
RD
WR
RST
INT
NC
RXLED
5362 drw 02
December 2004