IDT77V106L25TFI IDT, Integrated Device Technology Inc, IDT77V106L25TFI Datasheet - Page 7

• Manufacturer Part Number: IDT77V106L25TFI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V106L25TFI

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 1
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Among them is the fact that the output data bits can be represented by a set of
relatively simple symbols;
whether a timing marker command (X_8) or a start-of-cell command was sent
(X_X or X_4). If a start-of-cell command is detected, the next 53 bytes received
are decoded and forwarded to the descrambler. (See the TC Receive Block
Diagram).
The NRZI code transitions the wire voltage each time a ‘1’ bit is sent. This,
together with the previous encoding schemes guarantees that long run lengths
of either ‘0’ or ‘1’s are prevented. Each symbol is shifted out with its most
significant bit sent first.
active by continuing to transmit valid symbols. But it does not transmit another
start-of-cell command until it has another cell for transmission. The 77V106L25
never generates idle cells.
Transmit HEC Byte Calculation/Insertion
automatically across the first 4 bytes of the cell header, depending upon the
setting of bit 5 of the LED Driver and HEC Status/Control Register (0x03). This
byte is then either inserted as a replacement of the fifth byte transferred to the
PHY by the external system, or the cell is transmitted as received. A third
operating mode provides for insertion of “Bad” HEC codes which may aid in
communication diagnostics. These modes are controlled by the LED Driver
and HEC Status/Control Registers.
Receiver Description
reverse. The data is NRZI decoded before each symbol is reassembled. The
symbols are then sent to the 5b/4b decoder, followed by the Command Byte
Interpreter, De-Scrambler, and finally through a FIFO to the UTOPIA interface
to an ATM Layer device.
ATM Cell Format
Note that although the IDT77V106L25 can detect symbol and HEC errors, it
does not attempt to correct them
IDT77V106L25
This encode/decode implementation has several very desirable properties.
Run length is limited to <= 5;
Disparity never exceeds +/- 1.
On the receiver, the decoder determines from the received symbols
The output of the 4b/5b encoder provides serial data to the NRZI encoder.
When no cells are available to transmit, the 77V106L25 keeps the line
Byte #5 of each ATM cell, the HEC (Header Error Control) is calculated
The receiver side of the TC sublayer operates like the transmitter, but in
UDF = User Defined Field (or
HEC)
Bit 7
Payload Byte 48
Payload Byte 1
Header Byte 1
Header Byte 2
Header Byte 3
Header Byte 4
UDF
•
•
•
Bit 0
3505 drw 52
7
Good Signal Bit: Upon resetting the device or reestablishing a serial link,
logic in front of the 4b/5b decoder uses feedback from the 4b/ 5b decoder to
determine if it is not properly “framed” on the 5-bit symbols being received. If
not properly framed, it will shift its framing, one bit at a time, until it achieves proper
symbol framing. Receipt of an Escape (X) symbol will also force proper symbol
framing.
if the line is deemed ‘bad’. The Interrupt Status Register contains a Good Signal
Bit (bit 6, set to 0 = Bad signal initially) which shows the status of the line per
the following algorithm:
To declare ‘Good Signal’ (from “Bad” to “Good”)
7. When the clock ticks for 1,024 cycles (32MHz clock, 1,024 cycles = 204.8
symbols) and no “bad symbol” has been received, the counter decreases by
one. However, if at least one “bad symbol” is detected during these 1,024
clocks, the counter is increased by one, to a maximum of 7. The Good Signal
Bit is set to 1 when this counter reaches 0. The Good Signal Bit could be set
to 1 as quickly as 1,433 symbols (204.8 x 7) if no bad symbols have been
received
.
To declare ‘Bad Signal’ (from “Good” to “Bad”)
“Good” status). When the clock ticks for 1,024 cycles (32MHz clock, 1,024
cycles = 204.8 symbols) and there is at least one “bad symbol”, the counter
increases by one. If it detects all “good symbols” and no “bad symbols” in the
next time period, the counter decreases by one. The “Bad Signal” is declared
when the counter reaches 7. The Good Signal Bit could be set to 0 as quickly
as 1,433 symbols (204.8 x 7) if at least one “bad symbol” is detected in each
of seven consecutive groups of 204.8 symbols.
8kHz Timing Marker
which is essential for some applications requiring synchronization for voice or
video, and unnecessary for other applications. When unused, TXREF should
be tied high. Also note that it is not limited to 8kHz, should a different frequency
be desired. When looped, a received X_8 command byte causes one to be
generated on the transmit side.
A received X_8 command byte causes the 77V106L25 to issue a negative
pulse on RXREF.
The IDT77V106L25 monitors line conditions and can provide an interrupt
There is an up-down counter that counts from 7 to 0 and is initially set to
The same up-down counter counts from 0 to 7 (being at 0 to provide a
The 8kHz timing marker, described earlier, is a completely optional feature