77V126L200TFGI8 IDT, Integrated Device Technology Inc, 77V126L200TFGI8 Datasheet - Page 20

• Manufacturer Part Number: 77V126L200TFGI8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 77V126L200TFGI8

• Number Of Channels: 1
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Status and Control Register List
Master Control Register
Address: 0x00
Interrupt Status Register
Address: 0x01
IDT77V126L200
7
6
Bit Type
7
6
5
4
3
2
1
0
Nomenclature
“Reserved” register bits, if written, should always be written “0”
R/W = register may be read and written via the utility bus
R-only or W-only = register is read-only or write-only
sticky = register bit is cleared after the register containing it is read; all sticky bits are read-only
“0” = ‘cleared’ or ‘not set’
“1” = ‘set’
Bit Type
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0 = Bad Signal Good Signal Bit See definitions earlier in this data sheet.
Initial State
1 = discard
errored cells
0 = all interrupts Enable Cell Error Interrupts Only
0 = disabled
1 = discard
0 = not halted
0 = cell mode
1 = enable
interrupts
idle cells
Initial State
Reserved
1 - Good Signal
0 - Bad Signal
Reserved
Discard Receive Error Cells
On receipt of any cell with an error (e.g. short cell, invalid command mnemonic, receive HEC error (if enabled)), this
cell will be discarded and will not enter the receive FIFO.
If Bit 0 in this register is set (Interrupts Enabled), setting of this bit enables only "Received Cell Error" (as defined in bit
6) to trigger interrupt line."
Transmit Data Parity Check
Directs TC to check parity of TxDATA against parity bit located in TXPARITY.
Discard Received Idle Cells
Directs TC to discard received idle (VPI/VCI = 0 and GFC = 0) cells from PMD without signalling external systems.
Halt Tx
Halts transmission of data from TC to PMD and forces the TxD outputs to the "0" state."
UTOPIA Mode Select:
0 = cell mode, 1 = byte mode.
Enable Interrupt Pin (Interrupt Mask Bit)
Enables the INT output pin. If cleared, pin is always high and interrupt is masked. If set, an interrupt will be signaled
by setting the interrupt pin to "0". It doesn’t affect the Interrupt Status Registers."
Pulse PE-67583 or R4005
TDK TLA-6M103
Pulse R4005
Pulse ST6200T
Magnetics Module for 204.8 Mbps
Magnetics Modules for 25.6 Mbps
Magnetics Module for 51.2 Mbps
Table 5 Magnetics Modules
20 of 30
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Function
Function
December 2004