PXB4219EV34NP Infineon Technologies, PXB4219EV34NP Datasheet - Page 100

• Manufacturer Part Number: PXB4219EV34NP
• Manufacturer: Infineon Technologies

Specifications of PXB4219EV34NP

• Data Rate: 2.048Mbps
• Number Of Channels: 1
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

5.1.3
In these modes, transmit and receive channels are synchronized. Therefore, they may
be used for synchronization of frame and multiframe based protocols, e.g. Frame based
SDT on E1-Lines.
Only one central clock, the external reference clock RFCLK, is used to clock the data on
the different ports. Two synchronous modes working at 2.048 MHz and 8.192 MHz for
E1lines are available. T1 is not supported.
For each of these modes a submode exists, providing global or port specific
synchronization.
If global synchronization of all transmit and receive channels is desired, bit “symn” in
“opmo” has to be deasserted. In this case FRMFB[0] is used for frame and multiframe
synchronization in receive and transmit direction of all ports.
Port specific frame and multiframe synchronization of transmit and receive channels is
enabled if bit “symn” in “opmo” is set. In this case frame and multiframe synchronization
in receive and transmit direction of each port is based on the corresponding FRMFB.
After reset all outputs and input/output ports of the framer interface are in tristate mode.
They will be enabled by setting bit “p_tx_act” of the corresponding “Port Configuration
Register” (“pcfN”, see
5.1.3.1
In SYM2 mode the framer interface is clocked with a 2.048 MHz clock connected to
RFCLK. The mode is enabled by setting bit om = 11
All transmit and receive timeslots will be aligned to each other.
FRCLK[7:0]
FRDAT[7:0]
FRMFB[7:0]
Data Sheet
Synchronous Modes (SYM)
Synchronous Mode at 2.048 MHz (SYM2)
Framer Receive Clock
Unused
Framer Receive Data
depending on bit “frri” in “opmo”
0 =
1 =
Framer Receive Multiframe Begin
Depending on bits p_ces in pcfN:
0 =
1 =
depending on bit “rfpp” in “opmo”:
Chapter
7.1).
FRDAT is sampled with the falling edge of RFCLK
FRDAT is sampled with the rising edge of RFCLK
Structured CES: A pulse on this pin designates the
first frame of a new multiframe
Unstructured CES: Unused, no constant level
allowed
100
PXB 4219E, PXB 4220E, PXB 4221E
B
in “opmo”, see
Interface Description
Chapter 7.24
IWE8, V3.4
2003-01-20