77V126L200TFI IDT, Integrated Device Technology Inc, 77V126L200TFI Datasheet - Page 5

• Manufacturer Part Number: 77V126L200TFI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 77V126L200TFI

• Number Of Channels: 1
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

INT
OSC
RST
RXLED
RXREF
SE
SM
TXLED
TXREF
AGND
AVDO
GND
VDD
Signal Name Pin Number
Signal Name Pin Number
IDT77V126L200
34
52
35
33
1
49
64
3
2
50, 53, 55
51, 54, 56,
59
22, 44, 60
15, 28, 63
Out
In
In
Out
Out
In
In
Out
In
—
—
—
—
I/O
I/O
TTL line rate clock source, driven by a 100 ppm oscillator. 32 MHz for 25.6 Mbps; 64 MHz for 51.2 Mbps.
Transmit LED driver. Goes low for 223 cycles of OSC, beginning with TXSOC when a cell is received for transmission. 8 mA
Analog ground. AGND is ground the analog portion of the ship, which sources a more constant current than the digital por-
Signal Description
Interrupt. INT is an open-drain output, driven low to indicate an interrupt. Once low, INT remains low until the interrupt status
in the appropriate interrupt Status Register is read. Interrupt sources are programmable via the interrupt Mask Registers.
Reset. Active low asynchronous input resets all control logic, counters and FIFOs. A reset must be performed after power up
prior to normal operation of the part.
Receive LED driver. Driven low for 223 cycles of OSC, beginning with RXSOC when a good (non-null and non-errored) cell
is received. Drives 8 mA both high and low.
Receive Reference. Active low. RXREF pulses low for a programmable number of clock cycles when an X_8 command byte
is received.
Reserved signal. This input must be connected to logic low.
Reserved signal. This input must be connected to logic low.
drive current both high and low
Transmit Reference. At the falling edge of TXREF, an X_8 command byte is inserted into the transmit data stream. Typical
application is WAN timing.
Signal Description
tion.
Analog power supply. AVDD supplies power to the analog portion of the chip, which draws a more constant current than the
digital portion. 3.3 + 0.3V
Digital Ground.
Digital power supply. 3.3 + 0.3V.
Table 2 Signal Descriptions (Part 2 of 2)
Miscellaneous Signals
Power Supply Signals
5 of 30
December 2004