IDT77V106L25TF IDT, Integrated Device Technology Inc, IDT77V106L25TF Datasheet - Page 25

IDT77V106L25TF

Manufacturer Part Number
IDT77V106L25TF
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT77V106L25TF

Data Rate
25.6/51.2Mbps
Number Of Channels
1
Type Of Atm Phy Interface
UTOPIA
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
64
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant

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OSC, TXREF AND RESET TIMING
Note: The minimum RESET Pulse Width is either two RxCLK cycles, two TxCLK cycles, or two OSC cycles, whichever is greater (and applicable).
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
IDT77V106L25
Symbol
Trspw
Trrpw
Tcyc
Tckh
Tckl
Ttrh
Tcc
Ttrl
(51.2 Mbps)
OSC high time
OSC low time
OSC Cycle to cycle period variation
TXREF High time
TXREF Low time
Minimum RST Pulse Width
RXREF Pulse Width (For default setting in register 0x03
and 25.6 Mbps. Can be programmed for multiples
of this amount).
OSC cycle period (25.6 Mbps)
TXREF
RXREF
OSC
RST
See Figure 22
Gnd to 3.0V
Parameter
1.5V
1.5V
3ns
Figure 21. OSC, TXREF and Reset Timing
Tcyc
Trspw
25
Trrpw
two OSC cycles
Ttrl
Min.
0.9
30
15
40
40
35
35
Tckh
Tckl
(31.25ns)
15.625
D.U.T.
31.25
Typ
*Includes jig and scope capacitances.
1
Ttrh
900Ω
Figure 22. Output Load
3505 drw 45
Max
16.5
1.1
33
60
60
1
Receive
Data Bit
3.3V
Period
Unit
ns
ns
%
%
%
ns
ns
1.2KΩ
30pF*
Figure 22

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