IDT82V3012PV IDT, Integrated Device Technology Inc, IDT82V3012PV Datasheet - Page 7

• Manufacturer Part Number: IDT82V3012PV
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLLr

Specifications of IDT82V3012PV

• Number Of Elements: 1
• Supply Current: 60mA
• Pll Input Freq (min): 8KHz
• Pll Input Freq (max): 19.44MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SSOP
• Output Frequency Range: Up to 155.52MHz
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Pin Count: 56
• Lead Free Status / RoHS Status: Not Compliant

1
Pin Description
HOLDOVER
IDT82V3012
MODE_sel0
MODE_sel1
MON_out0
MON_out1
FREERUN
NORMAL
F0_sel0
F0_sel1
F1_sel0
F1_sel1
FLOCK
TIE_en
IN_sel
LOCK
Name
V
V
TCLR
OSCi
Fref0
Fref1
RST
V
DDA
DDD
SS
PIN DESCRIPTION
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) I
Power
Power
Power
Type
O
O
I
I
I
I
I
I
I
I
I
Pin Number
13, 19, 26
12, 18, 27
37, 48
38, 47
50
11
10
35
34
56
45
44
52
46
51
5
6
9
1
2
4
3
7
8
Ground.
0 V. All V
3.3 V Analog Power Supply.
Refer to
3.3 V Digital Power Supply.
Refer to
Oscillator Master Clock Input.
This pin is connected to a clock source.
Reference Input 0 and Reference Input 1.
These are two input reference sources (falling edge of 8 kHz, 1.544 MHz and 2.048 MHz or rising edge of 19.44
MHz) used for synchronization. The IN_sel pin determines which one of the two reference inputs to be used. See
Table - 4
The frequency of the reference inputs can be 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz. These two pins are
internally pulled up to V
Input Reference Selection.
A logic low at this pin selects Reference Input 0 (Fref0) and a logic high at this pin selects Reference Input 1 (Fref1).
The logic level on this input is gated in by the rising edges of F8o. This Pin is internally pulled down to V
Frequency Selection Inputs for Fref0.
These two inputs select one of the four possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) for the
Reference Input 0 (Fref0). See
Frequency Selection Inputs for Fref1.
These two inputs select one of the four possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) for the
Reference Input 1 (Fref1). These two pins are internally pulled down to V
Mode Selection Inputs.
These two inputs determine the operating mode of the IDT82V3012 (Normal, Holdover or Freerun). See
details.
The logic levels on these two pins are gated in by the rising edges of F8o. These two pins are internally pulled down
to V
Reset Input.
Pulling this pin to logic low for at least 300 ns will reset the IDT82V3012. While the RST pin is low, all framing and
clock outputs are at logic high.
To ensure proper operation, the device must be reset after it is powered up.
TIE Control Block Reset.
Pulling this pin to logic low for at least 300 ns will reset the TIE (Maximum Time Interval Error) control block and
result in a realignment of the output phase with the input phase. This pin is internally pulled up to V
TIE Control Block Enable.
A logic high at this pin enables the TIE control block while a logic low disables it. The logic level on this input is gated
in by the rising edges of F8o. This pin is internally pulled down to V
Fast Lock Mode Enable.
When this pin is set to logic high, the DPLL will quickly lock to the input reference within 500 ms.
Lock Indicator.
This output pin will go high when the DPLL is frequency locked to the input reference.
Holdover Indicator.
This output pin will go high whenever the DPLL enters Holdover mode.
Normal Indicator.
This output pin will go high whenever the DPLL enters Normal mode.
Freerun Indicator.
This output pin will go high whenever the DPLL enters Freerun mode.
Frequency Out-of-range Indicator for Fref0.
A logic high at this pin indicates that Fref0 is off the nominal frequency by more than ±12 ppm.
Frequency Out-of-range Indicator for Fref1.
A logic high at this pin indicates that Fref1 is off the nominal frequency by more than ±12 ppm.
SS
.
Chapter 2.11 Power Supply Filtering
Chapter 2.11 Power Supply Filtering
SS
for details.
pins should be connected to the ground.
DDD
.
Table - 2
7
T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
for details.
Techniques.
Techniques.
Description
ss
.
ss
. See
Table - 3
for details.
February 6, 2009
DDD
.
Table - 1
SS
.
for