ICS8545AG-02T IDT, Integrated Device Technology Inc, ICS8545AG-02T Datasheet

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ICS8545AG-02T

Manufacturer Part Number
ICS8545AG-02T
Description
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Driverr
Datasheet

Specifications of ICS8545AG-02T

Number Of Clock Inputs
2
Mode Of Operation
Single-Ended
Output Frequency
350MHz
Output Logic Level
LVDS
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.465V
Package Type
TSSOP
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Signal Type
LVCMOS/LVTTL
Mounting
Surface Mount
Pin Count
20
Lead Free Status / RoHS Status
Not Compliant
LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS
FANOUT BUFFER
Description
the ICS8545-02 provides a low power, low noise, solution for
distributing clock signals over controlled impedances of 100Ω. The
ICS8545-02 accepts an LVCMOS/LVTTL input level and translates
it to 3.3V LVDS output levels.
Guaranteed output and part-to-part skew characteristics make the
ICS8545-02 ideal for those applications demanding well defined
performance and repeatability.
Block Diagram
IDT™ / ICS™ LVDS FANOUT BUFFER
HiPerClockS™
CLK_SEL
ICS
CLK_EN
CLK1
CLK2
OE
Pullup
Pulldown
Pulldown
Pulldown
Pullup
The ICS8545-02 is a low skew, high performance
1-to-4 LVCMOS/LVTTL-to-LVDS Clock Fanout
Buffer and a member of the HiPerClockS™ family of
High Performance Clock Solutions from IDT.
Utilizing Low Voltage Differential Signaling (LVDS)
0
1
0
1
nD
LE
Q
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
1
Features
Four differential LVDS output pairs
Two LVCMOS/LVTTL clock inputs to support redundant
or selectable frequency fanout applications
Maximum output frequency: 350MHz
Translates LVCMOS/LVTTL input signals to LVDS levels
Output skew: 60ps (maximum)
Part-to-part skew: 450ps (maximum)
Propagation delay: 1.45ns (maximum)
Additive phase jitter, RMS: 0.14ps (typical)
Full 3.3Vsupply mode
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
6.5mm x 4.4mm x 0.925
CLK_SEL
CLK_EN
CLK1
CLK2
GND
GND
20-Lead TSSOP
V
OE
package body
DD
nc
nc
ICS8545-02
G Package
Top View
1
2
3
4
5
6
7
8
9
10
ICS8545AG-02 REV. A March 3, 2009
20
19
18
17
16
15
14
13
12
11
Q0
V
Q1
nQ1
nQ2
Q3
nQ0
Q2
nQ3
DD
mm
ICS8545-02

Related parts for ICS8545AG-02T

ICS8545AG-02T Summary of contents

Page 1

... Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Pin Assignment CLK_EN CLK_SEL Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 6.5mm x 4.4mm x 0.925 1 ICS8545-02 GND nQ0 CLK1 nQ1 CLK2 nQ2 GND nQ3 DD ICS8545-02 20-Lead TSSOP mm package body G Package Top View ICS8545AG-02 REV. A March 3, 2009 ...

Page 2

... Q3/nQ3. LVCMOS/LVTTL interface levels. Positive supply pins. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Test Conditions 2 Minimum Typical Maximum ICS8545AG-02 REV. A March 3, 2009 Units pF Ω k Ω k ...

Page 3

... Q0:Q3 0 LOW 1 HIGH IDT™ / ICS™ LVDS FANOUT BUFFER Inputs CLK_SEL Selected Source X 0 CLK1 1 CLK2 0 CLK1 1 CLK2 Disabled nQ0:nQ3 HIGH LOW 3 Outputs Q0:Q3 nQ0:nQ3 Hi-Z Hi-Z Low High Low High Active Active Active Active Enabled ICS8545AG-02 REV. A March 3, 2009 ...

Page 4

... DD A Test Conditions 4 + 0.5V Minimum Typical Maximum 3.135 3.3 3.465 90 Minimum Typical Maximum 0.3 DD -0.3 0.8 150 5 -5 -150 Minimum Typical Maximum 275 525 50 1.1 1.25 1 ICS8545AG-02 REV. A March 3, 2009 Units V mA Units V V µA µA µA µA Units ...

Page 5

... IDT™ / ICS™ LVDS FANOUT BUFFER = 3.3V ± 5 0°C to 70°C A Test Conditions 155.52MHz, Integration Range: 12kHz – 20MHz 20% to 80% ƒ ≤ 166MHz ƒ > 166MHz 5 Minimum Typical Maximum 350 1.0 1.45 0.14 60 450 150 700 ICS8545AG-02 REV. A March 3, 2009 Units MHz ...

Page 6

... Offset Frequency (Hz) device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. 6 ICS8545AG-02 REV. A March 3, 2009 ...

Page 7

... PW odc = t PERIOD Output Duty Cycle/Pulse Width/Period IDT™ / ICS™ LVDS FANOUT BUFFER SCOPE Qx nQ0:nQ3 Q0:Q3 nQx - Differential Output Level nQx Qx nQy Qy Output Skew CLK1, CLK2 nQ0:nQ3 Q0:Q3 x 100% Propagation Delay Cross Points PP GND tsk( ICS8545AG-02 REV. A March 3, 2009 V CMR ...

Page 8

... Parameter Measurement Information, continued 80% Clock 20% Outputs t R Output Rise/Fall Time V DD LVDS DC Input ➤ Offset Voltage Setup IDT™ / ICS™ LVDS FANOUT BUFFER 80 Input 20 Differential Output Voltage Setup out ➤ out LVDS 100 ICS8545AG-02 REV. A March 3, 2009 out ➤ ➤ out ...

Page 9

... All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, there should be no trace attached. For a multiple LVDS outputs buffer, if only partial outputs are used recommended to terminate the unused outputs 100 – 3.3V ICS8545AG-02 REV. A March 3, 2009 ...

Page 10

... IDT™ / ICS™ LVDS FANOUT BUFFER = 3. 3.465V, which gives worst case results 3.465V * 90mA = 311.85mW DD_MAX * Pd_total + for 20 Lead TSSOP, Forced Convection θ by Velocity JA 0 91.1°C/W 10 must be used. Assuming no air flow JA 1 2.5 86.7°C/W 84.6°C/W ICS8545AG-02 REV. A March 3, 2009 ...

Page 11

... All Dimensions in Millimeters Symbol Minimum 0.05 A2 0.80 b 0.19 c 0.09 D 6.40 E 6.40 Basic E1 4.30 e 0.65 Basic L 0.45 α 0° aaa Reference Document: JEDEC Publication 95, MO-153 11 2.5 84.6°C/W Maximum 1.20 0.15 1.05 0.30 0.20 6.60 4.50 0.75 8° 0.10 ICS8545AG-02 REV. A March 3, 2009 ...

Page 12

... LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Ordering Information Table 9. Ordering Information Part/Order Number Marking ICS8545AG-02 ICS8545AG-02 ICS8545AG-02T ICS8545AG-02 ICS8545AG-02LF ICS8545AG-02LF ICS8545AG-02LFT ICS8545AG-02LF NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. ...

Page 13

ICS8545-02 LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States ...

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