83948AYI-01LF IDT, Integrated Device Technology Inc, 83948AYI-01LF Datasheet
83948AYI-01LF
Specifications of 83948AYI-01LF
Related parts for 83948AYI-01LF
83948AYI-01LF Summary of contents
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... IAGRAM D CLK_EN Q LVCMOS_CLK 1 CLK 0 nCLK CLK_SEL OE 83948AYI-01 D IFFERENTIAL F EATURES 12 LVCMOS outputs Selectable LVCMOS clock or differential CLK, nCLK inputs CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL LVCMOS_CLK accepts the following input levels: LVCMOS or LVTTL ...
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... ABLE IN ESCRIPTIONS ABLE IN HARACTERISTICS 3A ABLE LOCK ELECT UNCTION 3B ABLE LOCK NPUT UNCTION ABLE — 0 — 0 — 0 — 0 — — 83948AYI-01 D IFFERENTIAL ABLE — — — — " www.icst.com/products/hiperclocks.html 2 ICS83948I- KEW - -LVCMOS F TO ANOUT REV. A OCTOBER 23, 2008 - UFFER " ...
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... T 4A ABLE OWER UPPLY HARACTERISTICS 4B ABLE HARACTERISTICS 83948AYI-01 D IFFERENTIAL 4.6V -0. 0 -0. 0.5V DDO 47.9°C/W (0 lfpm) -65°C to 150° 3.3V±0.3V -40° DDO 3.3V±0.3V -40° 85° DDO www.icst.com/products/hiperclocks.html 3 ICS83948I- KEW - -LVCMOS F TO ANOUT 85° ± REV. A OCTOBER 23, 2008 - UFFER ...
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... ABLE HARACTERISTICS 83948AYI-01 D IFFERENTIAL = 3.3V±0.3V -40° 85° DDO www.icst.com/products/hiperclocks.html 4 ICS83948I- KEW - -LVCMOS F TO ANOUT REV. A OCTOBER 23, 2008 - UFFER ...
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... P ARAMETER 1.65V±0.15V V DD, V DDO LVCMOS GND -1.65V±0.15V V DD nCLK CLK GND 83948AYI-01 D IFFERENTIAL M I EASUREMENT NFORMATION Qx 3. UTPUT OAD EST IRCUIT V Cross Points IFFERENTIAL NPUT EVEL www.icst.com/products/hiperclocks.html 5 ICS83948I- KEW TO - -LVCMOS ANOUT UFFER SCOPE V CMR REV. A OCTOBER 23, 2008 -12 ...
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... Qx Qy PART 1 Qx PART 2 Qy 0.8V Clock Outputs 83948AYI-01 D IFFERENTIAL V DDO 2 V DDO 2 tsk( UTPUT KEW V DDO 2 V DDO 2 tsk(pp ART TO ART KEW UTPUT ISE AND ALL IME www.icst.com/products/hiperclocks.html 6 ICS83948I- KEW TO - -LVCMOS ANOUT UFFER 2V 0. REV. A OCTOBER 23, 2008 -12 ...
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... LVCMOS_CLK nCLK CLK Q0:Q11 Q0:Q11 83948AYI-01 D IFFERENTIAL DDO ROPAGATION ELAY V V DDO DDO PERIOD t PW odc = t PERIOD t & ERIOD www.icst.com/products/hiperclocks.html 7 ICS83948I- KEW TO - -LVCMOS ANOUT UFFER V DDO 2 REV. A OCTOBER 23, 2008 -12 ...
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... R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609 IGURE 83948AYI-01 D IFFERENTIAL A I PPLICATION NFORMATION ...
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... Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs RANSISTOR OUNT The transistor count for ICS83948I-01 is: 1040 83948AYI-01 D IFFERENTIAL R I ELIABILITY NFORMATION q ...
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... ACKAGE UTLINE UFFIX ABLE ACKAGE EFERENCE OCUMENT 83948AYI-01 D IFFERENTIAL D IMENSIONS ° JEDEC P 95, MS-026 UBLICATION www.icst.com/products/hiperclocks.html 10 ICS83948I- KEW TO - -LVCMOS ANOUT UFFER ° REV. A OCTOBER 23, 2008 -12 ...
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... Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83948AYI-01 D IFFERENTIAL ...