ICS83948AYI-147LFT IDT, Integrated Device Technology Inc, ICS83948AYI-147LFT Datasheet
ICS83948AYI-147LFT
Specifications of ICS83948AYI-147LFT
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ICS83948AYI-147LFT Summary of contents
Page 1
... Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Pin Assignment CLK_SEL Q0 LVCMOS_CLK Q1 CLK nCLK Q2 CLK_EN GND 7mm x 7mm x 1.4mm package body Q10 Q11 1 ICS83948I-147 GND DDO GND DDO ICS83948I-147 32-Lead LQFP Y Package Top View ICS83948AYI-147 REV. D APRIL 8, 2009 ...
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... Output enable pin. When LOW, outputs are in an High-impedance state. Input Pullup when HIGH, outputs are active. LVCMOS/LVTTL interface levels. Power supply pin. Power supply ground. Single-ended clock outputs. LVCMOS/LVTTL interface levels. Output supply pins. Test Conditions 2 Minimum Typical Maximum ICS83948AYI-147 REV. D APRIL 8, 2009 Units pF Ω k Ω Ω ...
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... A Minimum Typical Maximum 3.135 3.3 3.465 3.135 3.3 3.465 55 = -40°C to 85°C A Minimum Typical Maximum 2.375 2.5 2.625 2.375 2.5 2.625 52 ICS83948AYI-147 REV. D APRIL 8, 2009 Polarity Non-Inverting Non-Inverting Non-Inverting Non-Inverting Inverting Inverting Non-Inverting Non-Inverting Units Units ...
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... A Minimum Typical Maximum 3.135 3.3 3.465 2.375 2.5 2.625 Minimum Typical Maximum 1 -0.3 -0.3 2.4 1.8 0.15 GND + 0 Ω /2. DDO ICS83948AYI-147 REV. D APRIL 8, 2009 Units Units + 0 0.3 V 0.8 V 0.7 V 300 µ 0.55 V 0.30 V 0.6 V 1.3 V – 0.85 V ...
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... Measured on the Rising Edge @ V Measured on the Rising Edge @ V 0. ƒ ≤ 150MHz, Ref = CLK/nCLK /2 of the output. DDO /2 of the output. DDO DDO 5 Minimum Typical Maximum Units 2 2 0.14 /2 DDO /2 DDO 0 /2. ICS83948AYI-147 REV. D APRIL 8, 2009 350 MHz 100 1 /2. DDO ...
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... V Measured on the Rising Edge @ V 0.6V to 1.8V ƒ ≤ 150MHz, Ref = CLK/nCLK /2 of the output. DDO /2 of the output. DDO DDO 6 Minimum Typical Maximum Units 1.5 1.7 0.14 /2 DDO /2 DDO 0 /2. ICS83948AYI-147 REV. D APRIL 8, 2009 350 MHz 4 160 1 /2. ...
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... Measured on the Rising Edge @ V 0. ƒ ≤ 200MHz, Ref = CLK/nCLK /2 of the output. DDO /2 of the output. DDO DDO 7 = -40°C to 85°C A Minimum Typical Maximum Units 2 2 0.14 /2 DDO /2 DDO 0 /2. ICS83948AYI-147 REV. D APRIL 8, 2009 350 MHz 100 1 /2. DDO ...
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... Offset From Carrier Frequency (Hz) device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. 8 Additive Phase Jitter, RMS 0.14ps (typical) ICS83948AYI-147 REV. D APRIL 8, 2009 ...
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... IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 1.25V±5% SCOPE V DD, V DDO Qx LVCMOS GND -1.25V±5% 2.5V Core/2.5V LVCMOS Output Load AC Test Circuit V DD SCOPE nCLK Qx CLK GND Differential Input Level Qx Qy Output Skew 9 SCOPE Cross Points PP V DDO 2 V DDO 2 tsk(o) ICS83948AYI-147 REV. D APRIL 8, 2009 CMR ...
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... DD 2 CLK nCLK CLK V DDO 2 Q0:Q11 ➤ ➤ Propagation Delay IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 2V 0.8V Q0:Q11 t F 2.5V Output Rise/Fall Time Q0:Q11 Output Duty Cycle/Pulse Width/Period 10 1.8V 1.8V 0. DDO PERIOD 100% odc = t PERIOD ICS83948AYI-147 REV. D APRIL 8, 2009 0.6V ...
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... A 1kΩ resistor can be used. IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR / Single Ended Clock Input Figure 1. Single-Ended Signal Driving Differential Input Outputs: LVCMOS Outputs All unused LVCMOS output can be left floating. There should be no trace attached CLK V_REF nCLK C1 0. ICS83948AYI-147 REV. D APRIL 8, 2009 ...
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... Zo = 50Ω R1 100 Zo = 50Ω LVDS Driven by a 3.3V LVDS Driver 2. 120 120 Zo = 60Ω 60Ω SSTL R1 R2 120 120 Driven by a 2.5V SSTL Driver ICS83948AYI-147 REV. D APRIL 8, 2009 3.3V CLK nCLK HiPerClockS Input 3.3V CLK nCLK Receiver 3.3V CLK nCLK HiPerClockS ...
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... Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count for ICS83948I-147 is: 1040 Pin compatible with the MPC9448 IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR θ vs. Air Flow 73.6°C/W 63.9°C/W 13 2.5 60.3°C/W ICS83948AYI-147 REV. D APRIL 8, 2009 ...
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... D & E 9.00 Basic D1 & E1 7.00 Basic D2 & E2 5.60 Ref. e 0.80 Basic L 0.45 0.60 θ 0° ccc Reference Document: JEDEC Publication 95, MS-026 IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR Maximum 1.60 0.15 1.45 0.45 0.20 0.75 7° 0.10 14 ICS83948AYI-147 REV. D APRIL 8, 2009 ...
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... Shipping Packaging 32 Lead LQFP 32 Lead LQFP 1000 Tape & Reel “Lead-Free” 32 Lead LQFP “Lead-Free” 32 Lead LQFP 1000 Tape & Reel 15 Temperature Tray -40°C to 85°C -40°C to 85°C Tray -40°C to 85°C -40°C to 85°C ICS83948AYI-147 REV. D APRIL 8, 2009 ...
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... Added Mix DC Characteristics Power Supply Table. Added Mix AC Characteristics Table. Parameter Measurement Information Section - added 3.3V/2.5V LVCMOS Output Load AC Test Circuit diagram. Ordering Information Table - deleted ICS prefix from Part/Order Number column. 16 from 4pF max. to 4pF typical; and IN . ICS83948AYI-147 REV. D APRIL 8, 2009 Date 11/21/05 1/15/08 4/1/09 ...
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ICS83948I-147 LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER Contact Information: www.IDT.com Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT © 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT ...