ICS87322BYIT IDT, Integrated Device Technology Inc, ICS87322BYIT Datasheet - Page 7

• Manufacturer Part Number: ICS87322BYIT
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Dividerr

Specifications of ICS87322BYIT

• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 750MHz
• Output Logic Level: ECL/LVPECL
• Operating Supply Voltage (min): -3/3V
• Operating Supply Voltage (typ): -3.3/3.3V
• Operating Supply Voltage (max): -3.8/3.8V
• Package Type: LQFP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: CML/LVDS/LVPECL/SSTL
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Not Compliant

W
87322BYI
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
T
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
RTT =
ERMINATION FOR
IRING THE
((V
F
FOUT
OH
IGURE
+ V
D
OL
3A. LVPECL O
IFFERENTIAL
) / (V
1
CC
3.3V LVPECL O
Z
Z
– 2)) – 2
o
o
= 50Ω
= 50Ω
F
I
IGURE
Z
NPUT TO
o
50Ω
Single Ended Clock Input
UTPUT
2. S
A
T
RTT
A
ERMINATION
50Ω
INGLE
UTPUTS
PPLICATION
CCEPT
V
CC
E
C1
0.1u
FIN
- 2V
NDED
V_REF
S
INGLE
CC
www.idt.com
S
/2 is
IGNAL
E
7
I
NDED
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
and R2/R1 = 0.609.
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
NFORMATION
1K
D
R1
1K
R2
RIVING
VCC
3.3V LVPECL/ECL C
L
FOUT
EVELS
CLK
nCLK
F
D
IGURE
IFFERENTIAL
3B. LVPECL O
Z
Z
o
o
I
= 50Ω
= 50Ω
NPUT
CC
125Ω
84Ω
= 3.3V, V_REF should be 1.25V
L
UTPUT
ICS87322BI
OW
3.3V
LOCK
125Ω
84Ω
S
T
ERMINATION
REV. C OCTOBER 13, 2010
KEW
G
FIN
ENERATOR
, ÷1/÷2,