ICS85314AMI-11T IDT, Integrated Device Technology Inc, ICS85314AMI-11T Datasheet

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ICS85314AMI-11T

Manufacturer Part Number
ICS85314AMI-11T
Description
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Driverr
Datasheet

Specifications of ICS85314AMI-11T

Number Of Clock Inputs
2
Mode Of Operation
Differential
Output Frequency
700MHz
Output Logic Level
LVPECL
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.8V
Package Type
SOIC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
20
Lead Free Status / RoHS Status
Not Compliant
Block Diagram
nCLK_EN
General Description
clock enable is internally synchronized to eliminate runt clock pulses
on the outputs during asynchronous assertion/deassertion of the
clock enable pin.
Guaranteed output and part-to-part skew characteristics make the
ICS85314I-11 ideal for those applications demanding well defined
performance and repeatability.
CLK_SEL
ICS85314AGI-11 REVISION E MAY 4, 2010
HiPerClockS™
ICS
nCLK0
nCLK1
CLK0
CLK1
Pulldown
Pulldown
Pullup
Pullup
Pulldown
Pulldown
The ICS85314I-11 is a low skew, high performance
1-to-5 Differential-to-2.5V/3.3V LVPECL fanout buffer.
The ICS85314I-11 has two selectable differential clock
inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs can
accept most standard differential input levels. The
0
1
Low Skew, 1-to-5 Differential-to-2.5V, 3.3V
LVPECL Fanout Buffer
CK
D
Q
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
1
Features
Five differential 2.5V/3.3V LVPECL outputs
Selectable differential CLKx, nCLKx inputs
CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the following
differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Maximum output frequency: 700MHz
Translates any single-ended input signal to 3.3V
LVPECL levels with resistor bias on nCLK input
Output skew: 30ps (maximum)
Propagation delay: 1.8ns (maximum)
RMS phase jitter @ 155.52MHz (12kHz - 20MHz):
0.05ps (typical)
LVPECL mode operating voltage supply range:
V
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
CC
= 2.375V to 3.8V, V
6.5mm x 4.4mm x 0.92mm package body
7.5mm x 12.8mm x 2.3mm package body
Pin Assignment
nQ0
nQ1
nQ2
nQ3
nQ4
20-Lead TSSOP
Q0
Q2
Q3
Q4
Q1
20-Lead SOIC
ICS85314I-11
ICS85314I-11
EE
G Package
M Package
Top View
Top View
= 0V
1
2
3
4
5
6
7
8
9
10
©2010 Integrated Device Technology, Inc.
20
19
18
17
16
15
14
13
12
11
V
nCLK_EN
V
nCLK1
CLK1
RESERVED
nCLK0
CLK_SEL
V
CC
CC
EE
ICS85314I-11
DATA SHEET

Related parts for ICS85314AMI-11T

ICS85314AMI-11T Summary of contents

Page 1

Low Skew, 1-to-5 Differential-to-2.5V, 3.3V LVPECL Fanout Buffer General Description The ICS85314I- low skew, high performance ICS 1-to-5 Differential-to-2.5V/3.3V LVPECL fanout buffer. The ICS85314I-11 has two selectable differential clock HiPerClockS™ inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs ...

Page 2

ICS85314I-11 Data Sheet Table 1. Pin Descriptions Number Name 1, 2 Q0, nQ0 Output 3, 4 Q1, nQ1 Output 5, 6 Q2, nQ2 Output 7, 8 Q3, nQ3 Output 9, 10 Q4, nQ4 Output 11 V Power EE 12 CLK_SEL ...

Page 3

ICS85314I-11 Data Sheet Function Tables Table 3A. Control Input Function Table Inputs nCLK_EN CLK_SEL After nCLK_EN switches, the clock outputs are disabled or enabled following a falling input clock edge as shown ...

Page 4

ICS85314I-11 Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those ...

Page 5

ICS85314I-11 Data Sheet Table 4D. LVPECL DC Characteristics, V Symbol Parameter V Output High Voltage; NOTE Output Low Voltage; NOTE Peak-to-Peak Output Voltage Swing SWING NOTE 1: Outputs termination with 50Ω ...

Page 6

ICS85314I-11 Data Sheet Typical Phase Noise at 155.52MHz 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 ICS85314AGI-11 REVISION E MAY 4, 2010 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL ...

Page 7

ICS85314I-11 Data Sheet Parameter Measurement Information LVPECL V EE -1.8V to -0.375V LVPECL Output Load AC Test Circuit nQx nQx nQy nQy tsk(o) Output Skew nCLK[0:1] CLK[0:1] nQ[0:4] Q[0: Propagation Delay ICS85314AGI-11 REVISION E MAY ...

Page 8

ICS85314I-11 Data Sheet Parameter Measurement Information nCLK[0:1] CLK[0:1] nCLK_EN t t SET-UP HOLD Setup & Hold Time nQ[0:4] Q[0: PERIOD t PW odc = t PERIOD Output Duty Cycle ICS85314AGI-11 REVISION E MAY 4, 2010 LOW SKEW, ...

Page 9

ICS85314I-11 Data Sheet Application Information Wiring the Differential Input to Accept Single-Ended Levels Figure 2 shows how a differential input can be wired to accept single ended levels. The reference voltage V REF the bias resistors R1 and R2. The ...

Page 10

ICS85314I-11 Data Sheet Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V and V SWING V input requirements. Figures show interface examples CMR for the CLK/nCLK input ...

Page 11

ICS85314I-11 Data Sheet Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that ...

Page 12

ICS85314I-11 Data Sheet Termination for 2.5V LVPECL Outputs Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω – 2V. For V = 2.5V, the ...

Page 13

ICS85314I-11 Data Sheet Power Considerations This section provides information on power dissipation and junction temperature for the ICS85314I-11. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85314I-11 is the sum of the ...

Page 14

ICS85314I-11 Data Sheet 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pairs. LVPECL output driver circuit and termination are shown in Figure Figure 6. LVPECL ...

Page 15

ICS85314I-11 Data Sheet Reliability Information Table 7A. θ vs. Air Flow Table for a 20 Lead SOIC, Forced Convection JA Linear Feet per Minute Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB ...

Page 16

ICS85314I-11 Data Sheet Package Outlines and Package Dimensions Package Outline - G Suffix for 20 Lead TSSOP Table 8A. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 ...

Page 17

... ICS85314AMI-11LF 85314AMI-11LFT ICS85314AMI-11LF NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use ...

Page 18

ICS85314I-11 Data Sheet Revision History Sheet Rev Table Page T1 2 Pin Description Table - Pin 14 & 17, nCLKx, deleted partial description and added Pullup in the “Type” column Pin Characteristics Table - CIN changed 4pF max. ...

Page 19

ICS85314I-11 Data Sheet 6024 Silver Creek Valley Road Sales 800-345-7015 (inside USA) San Jose, California 95138 +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications ...

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