ICS87322BYI IDT, Integrated Device Technology Inc, ICS87322BYI Datasheet
ICS87322BYI
Specifications of ICS87322BYI
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ICS87322BYI Summary of contents
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G D ENERAL ESCRIPTION The ICS87322BI is a low skew, ÷1/÷2 3.3V LVPECL/ECL Clock Generator. Using multiplexed/redundant clock inputs the ICS87322BI is designed to translate most differential signal levels to LVPECL/ECL levels. The CLK_SEL input selects between CLK0, nCLK0 and ...
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ABLE IN ESCRIPTIONS ...
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ABLE IN HARACTERISTICS ...
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BSOLUTE AXIMUM ATINGS Supply Voltage Inputs Outputs Continuous Current Surge Current Package Thermal Impedance, θ JA Storage Temperature, T STG T 4A ABLE OWER UPPLY HARACTERISTICS S ...
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ABLE HARACTERISTICS ...
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P ARAMETER CCO LVPECL V EE -1.8V to -1. UTPUT OAD EST IRCUIT nQx Qx nQy Qy tsk( UTPUT KEW nQXx QXx nQXy QXy tsk(b) Where X = ...
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IRING THE IFFERENTIAL NPUT TO Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V generated by the bias resistors R1, R2 and C1. This bias ...
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LVPECL LOCK NPUT NTERFACE The CLK /nCLK accepts LVPECL, CML, SSTL and other differential signals. Both V and V SWING and V input requirements. Figures show CMR interface examples for the CLK/nCLK input driven ...
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S E CHEMATIC XAMPLE Figure 5 shows a schematic example of the ICS87322BI. In this example, the CLK0/nCLK0 input is selected. The input is driven by an LVPECL driver. All banks are set at ÷2. The decoupling VCC SP = ...
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This section provides information on power dissipation and junction temperature for the ICS87322BI. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS87322BI is the sum of the core power plus the power ...
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Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure calculate worst case power dissipation into the load, use ...
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ABLE VS IR LOW ABLE FOR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row ...
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ACKAGE UTLINE UFFIX FOR ABLE θ θ θ θ θ ...
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ABLE RDERING NFORMATION ...
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We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of ...