ICS870S208BK IDT, Integrated Device Technology Inc, ICS870S208BK Datasheet

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ICS870S208BK

Manufacturer Part Number
ICS870S208BK
Description
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Dividerr
Datasheet

Specifications of ICS870S208BK

Number Of Clock Inputs
2
Mode Of Operation
Differential
Output Frequency
250MHz
Output Logic Level
LVCMOS/LVTTL
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.465V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
32
Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS870S208BKLF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
ICS870S208BKLFT
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER W/
DIVIDER AND GLITCHLESS SWITCH
G
variety of differential input types. The device provides the cap-
ability to suppress any glitch at the outputs of the device during
an input clock switch to enhance clock redundancy in fault tole-
rant applications. The low impedance LVCMOS outputs are
designed to drive 50Ω series or parallel terminated transmission
lines. The effective fanout can be increased from 8 to 16 by utilizing
the ability of the outputs to drive two series terminated lines. The
divide select inputs, DIV_SELA and DIV_SELB, control the output
frequency of each bank. The output banks can be independently
selected for ÷1 or ÷2 operation. The output enable pins assigned
to each output, support enabling and disabling of each output
individually.
The ICS870S208 is characterized at full 3.3V and 2.5V, and mixed
3.3V/2.5V output operating supply modes. Guaranteed output and
part-to-part skew characteristics make the ICS870S208 ideal for
high performance, single ended applications.
B
DIV_SELA
DIV_SELB
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT
CLK_SEL
HiPerClockS™
IC S
LOCK
nCLK0
nCLK1
ENERAL
CLK0
CLK1
/ ICS
Pulldown
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Pulldown
LVCMOS FANOUT BUFFER W/DIVIDER
D
The ICS870S208 is a low skew, 8 output LVCMOS /
LVTTL Fanout Buffer with selectable divider and a
member of the HiPerClockS™ family of High
Perfor mance Clock Solutions from IDT. The
ICS870S208 has 2 selectable inputs that accept a
IAGRAM
D
ESCRIPTION
0
1
÷1
÷2
0
1
0
1
QA0
OE_A0
QA1
OE_A1
QA2
OE_A2
QA3
OE_A3
QB0
OE_B0
QB1
OE_B1
QB2
OE_B2
QB3
OE_B3
1
F
• Eight LVCMOS/LVTTL outputs (2 banks of 4 outputs)
• Two selectable differential CLKx/nCLKx clock inputs
• Dual differential input pairs can accept the following differen-
• Maximum output frequency: 250MHz
• Independent bank control for ÷1 or ÷2 operation
• Glitchless output behavior during input switch
• Output skew: 50ps (typical) @ 3.3V
• Bank skew: 30ps (typical) @ 3.3V
• Supply modes:
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
Each output has individual synchronous output enable
tial input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Core/Output
3.3V/3.3V
2.5V/2.5V
3.3V/2.5V
packages
EATURES
P
DIV_SELB
DIV_SELA
CLK_SEL
IN
nCLK0
nCLK1
CLK0
CLK1
V
A
DD
SSIGNMENT
1
2
3
4
5
6
7
8
5mm x 5mm x 0.925mm
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
32-Lead VFQFN
ICS870S208
ICS870S208BK REV. A NOVEMBER 9, 2007
package body
K Package
Top View
PRELIMINARY
ICS870S208
24
23
22
21
20
19
18
17
OE_B3
OE_B2
OE_B1
OE_B0
OE_A3
OE_A2
OE_A1
OE_A0

Related parts for ICS870S208BK

ICS870S208BK Summary of contents

Page 1

... OE_A3 nCLK1 QB0 DIV_SELA OE_B0 QB1 0 OE_B1 QB2 1 OE_B2 QB3 OE_B3 1 PRELIMINARY ICS870S208 A SSIGNMENT OE_B3 2 23 OE_B2 3 22 OE_B1 OE_B0 OE_A3 6 19 OE_A2 7 18 OE_A1 8 OE_A0 ICS870S208 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View ICS870S208BK REV. A NOVEMBER 9, 2007 ...

Page 2

... This is shown in Figure 1A. F 1A. CLK_SEL T D IGURE IMING IAGRAM F 1B. DIV_SEL T D IGURE X IMING IAGRAM Hi low state to ensure a clean rising edge of the first output clock IGURE X IMING IAGRAM 2 PRELIMINARY ICS870S208BK REV. A NOVEMBER 9, 2007 ...

Page 3

... OEx is low, the output will transition from the HighZ to a low state to ensure a clean rising edge of the first output clock when the Oex is pulled high again IGURE X WITH AD NPUT 3 PRELIMINARY T D NPUT IMING IAGRAM NPUT IMING IAGRAM T D IMING IAGRAM ICS870S208BK REV. A NOVEMBER 9, 2007 ...

Page 4

... Although no glitches will occur, due to the unknown state of the failing clock, a transition may take up to 1us to execute. Input Bad F 1G. CLK_SEL B IGURE WITH NPUT IMING IAGRAM ICS870S208BK REV. A NOVEMBER 9, 2007 PRELIMINARY ...

Page 5

... ICS870S208 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER W/DIVIDER AND GLITCHLESS SWITCH ABLE IN HARACTERISTICS ABLE UNCTION ABLE IDT ™ / ICS ™ LVCMOS FANOUT BUFFER W/DIVIDER PRELIMINARY kΩ kΩ Ω ICS870S208BK REV. A NOVEMBER 9, 2007 ...

Page 6

... Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability 3.3V±5 DDOA DDOB 2.5V±5 DDOA DDOB 3.3V±5 DDOA DDOB PRELIMINARY = 0°C 70° 0°C 70° 2.5V±5 0°C 70° ICS870S208BK REV. A NOVEMBER 9, 2007 ...

Page 7

... ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± 3.3V±5% 2.5V±5 PRELIMINARY " " -40°C 85° ICS870S208BK REV. A NOVEMBER 9, 2007 µ A µ A µ A µ A µ A µ A µ A µ µ A µ A µ A µ ...

Page 8

... ICS870S208 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER W/DIVIDER AND GLITCHLESS SWITCH T 5A ABLE HARACTERISTICS 5B ABLE HARACTERISTICS IDT ™ / ICS ™ LVCMOS FANOUT BUFFER W/DIVIDER = 3.3V±5 0° DDOA DDOB 2.5V±5 0° DDOA DDOB 70° 70° ICS870S208BK REV. A NOVEMBER 9, 2007 PRELIMINARY ...

Page 9

... ICS870S208 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER W/DIVIDER AND GLITCHLESS SWITCH T 5C 3.3V±5%, V ABLE HARACTERISTICS IDT ™ / ICS ™ LVCMOS FANOUT BUFFER W/DIVIDER = V = 2.5V±5%, T DDOA DDOB PRELIMINARY = 0°C 70° ICS870S208BK REV. A NOVEMBER 9, 2007 ...

Page 10

... SCOPE nCLK0, Qx nCLK1 CLK0, CLK1 GND C D IRCUIT IFFERENTIAL QX0:QX0 QX0:QX0 B S ANK KEW 10 PRELIMINARY I NFORMATION SCOPE Qx /2. UTPUT OAD EST IRCUIT V Cross Points NPUT EVEL V DDOX 2 V DDOX 2 tsk(b) ( where X denotes outputs in the same bank ICS870S208BK REV. A NOVEMBER 9, 2007 V CMR ) ...

Page 11

... KEW 80% 20% Clock t Outputs UTPUT ISE ALL IME IDT ™ / ICS ™ LVCMOS FANOUT BUFFER W/DIVIDER UTPUT KEW 80% QA0:QA3, QB0:QB3 20 UTPUT UTY 11 PRELIMINARY V DDOX 2 V DDOX 2 tsk(o) V DDOX PERIOD t PW odc = x 100% t PERIOD YCLE ULSE IDTH ERIOD ICS870S208BK REV. A NOVEMBER 9, 2007 ...

Page 12

... Single Ended Clock Input V_REF C1 0. INGLE NDED IGNAL RIVING O P NPUT AND UTPUT INS O UTPUTS LVCMOS O All unused LVCMOS output can be left floating. There should be no trace attached. 12 PRELIMINARY = 3.3V, V_REF should be 1.25V DD CLKx nCLKx D I IFFERENTIAL NPUT : UTPUTS ICS870S208BK REV. A NOVEMBER 9, 2007 ...

Page 13

... LVDS_Driv er R1 100 Ohm 3D CLK/nCLK LOCK NPUT D 3.3V LVDS D RIVEN BY A RIVER 2. 120 120 Zo = 60Ω CLK Zo = 60Ω nCLK R1 R2 120 120 3F CLK/nCLK LOCK NPUT D 2.5V SSTL D RIVEN BY A RIVER ICS870S208BK REV. A NOVEMBER 9, 2007 PRELIMINARY 3.3V CLK nCLK Receiv er 3.3V HiPerClockS ...

Page 14

... Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadfame Base Package, Amkor Technology. EXPOSED HEAT SLUG THERMAL VIA XPOSED AD HERMAL ELEASE ATH 14 PRELIMINARY SOLDER PIN LAND PATTERN PIN PAD (GROUND PAD) – IDE IEW RAWING NOT TO CALE ICS870S208BK REV. A NOVEMBER 9, 2007 ...

Page 15

... The transistor count for ICS870S208 is: 2788 IDT ™ / ICS ™ LVCMOS FANOUT BUFFER W/DIVIDER R I ELIABILITY NFORMATION 32 L VFQFN EAD θ θ θ θ θ vs. Air Flow (Meters per Second 49.5°C/W 15 PRELIMINARY 1 2.5 43.3°C/W 38.8°C/W ICS870S208BK REV. A NOVEMBER 9, 2007 ...

Page 16

... IDT ™ / ICS ™ LVCMOS FANOUT BUFFER W/DIVIDER VFQFN EAD this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 8 below ABLE ACKAGE IMENSIONS Reference Document: JEDEC Publication 95, MO-220 16 PRELIMINARY ICS870S208BK REV. A NOVEMBER 9, 2007 ...

Page 17

... IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS ™ LVCMOS FANOUT BUFFER W/DIVIDER " " " " " " PRELIMINARY ° & ° ° & ° ICS870S208BK REV. A NOVEMBER 9, 2007 ° ° ° ° ...

Page 18

ICS870S208 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER W/DIVIDER AND GLITCHLESS SWITCH Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United ...

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