ICS8702BY IDT, Integrated Device Technology Inc, ICS8702BY Datasheet

ICS8702BY

Manufacturer Part Number

ICS8702BY

Description

Manufacturer

IDT, Integrated Device Technology Inc

Type

Clock Dividerr

Datasheet

1.ICS8702BY.pdf (14 pages)

Specifications of ICS8702BY

Number Of Clock Inputs

Mode Of Operation

Differential

Output Frequency

250MHz

Output Logic Level

LVCMOS/LVTTL

Operating Supply Voltage (min)

3.135V

Operating Supply Voltage (typ)

3.3V

Operating Supply Voltage (max)

3.465V

Package Type

TQFP

Operating Temp Range

0C to 70C

Operating Temperature Classification

Commercial

Mounting

Surface Mount

Pin Count

Lead Free Status / RoHS Status

Not Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

ICS8702BY

Manufacturer:

ICS

Quantity:

673

Company:

BOSTOCK HK LIMITED

Part Number:

ICS8702BYLF

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

Company:

BOSTOCK HK LIMITED

Part Number:

ICS8702BYLFT

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

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8702BY

The ICS8702 is a low skew, ÷1, ÷2 Differential-to-LVCMOS

Clock Generator. The ICS8702 is designed to translate any

differential signal levels to LVCMOS/LVTTL levels. True or

inverting, single-ended to LVCMOS translation can be

achieved with a resistor bias on the nCLK or CLK inputs,

respectively. The effective fan-out can be increased from 20

to 40 by utilizing the ability of the outputs to drive two series

terminated lines.

The divide select inputs, DIV_SELx, control the output

frequency of each bank. The outputs can be utilized in the

÷1, ÷2 or a combination of ÷1 and ÷2 modes. The bank

enable inputs, BANK_EN0:1, supports enabling and

disabling each bank of outputs individually. The master reset

input, nMR/OE, resets the internal frequency dividers and

also controls the enabling and disabling of all outputs

simultaneously.

The ICS8702 is characterized at 3.3V and mixed 3.3V input

supply, and 2.5V output supply operating modes. Guaranteed

bank, output, multiple frequency and part-to-part skew

characteristics make the ICS8702 ideal for those clock

dis-tribution applications demanding well defined performance

and repeatability.

LOCK

ENERAL

BANK_EN0

BANK_EN1

DIV_SELC

DIV_SELD

DIV_SELA

DIV_SELB

nMR/OE

nCLK

CLK

IAGRAM

ESCRIPTION

÷ 1

÷ 2

Bank Enable

Logic

QA0:QA4

QB0:QB4

QC0:QC4

QD0:QD4

IFFERENTIAL

www.idt.com

• Twenty LVCMOS outputs, 7Ω typical output impedance

• One differential clock input pair

• CLK, nCLK supports the following input types:

• Maximum output frequency: 250MHz

• Translates any differential input signal (LVPECL, LVHSTL,

• Translates any single-ended input signal to LVCMOS levels

• Bank enable logic allows unused banks to be disabled in

• Output skew: 200ps (maximum)

• Bank skew: 150ps (maximum)

• Part-to-part skew: 650ps (maximum)

• Multiple frequency skew: 250ps (maximum)

• 3.3V or mixed 3.3V input, 2.5V output operating

• 0°C to 70°C ambient operating temperature

• Other divide values available on request

• Available in both standard and lead-free RoHS compliant

LVDS, LVPECL, LVHSTL, SSTL, HCSL

LVDS) to LVCMOS levels without external bias networks

with a resistor bias on nCLK input

reduced fanout applications

supply modes

packages

EATURES

-LVCMOS/LVTTL C

GND

QC3

QC4

QD0

QD1

QD2

QD3

QD4

DDO

SSIGNMENT

48 47 46 45 44 43 42 41 40 39 38 37

13 14 15 16 17 18 19 20 21 22 23 24

7mm x 7mm x 1.4mm

48-Lead LQFP

ICS8702

Y Package

Top View

LOCK

ICS8702

KEW

REV. E JULY 25, 2010

ENERATOR

, ÷1, ÷2

QB1

QB0

QA4

QA3

GND

QA2

GND

QA1

QA0

DDO

Related parts for ICS8702BY

ICS8702BY Summary of contents

Page 1

G D ENERAL ESCRIPTION The ICS8702 is a low skew, ÷1, ÷2 Differential-to-LVCMOS Clock Generator. The ICS8702 is designed to translate any differential signal levels to LVCMOS/LVTTL levels. True or inverting, single-ended to LVCMOS translation can be achieved with a ...

Page 2

ABLE IN ESCRIPTIONS ...

Page 3

T 3A ABLE ONTROL NPUT UNCTION ...

Page 4

BSOLUTE AXIMUM ATINGS Supply Voltage Inputs Outputs Package Thermal Impedance, θ JA Storage Temperature, T STG T 4A ABLE OWER UPPLY HARACTERISTICS ...

Page 5

T 4D. LVCMOS/LVTTL DC C ABLE HARACTERISTICS ...

Page 6

T 5A ABLE HARACTERISTICS ...

Page 7

T 5B ABLE HARACTERISTICS ...

Page 8

P ARAMETER 1.65V± DDO LVCMOS GND -1.165V±5% 3.3V C /3. ORE UTPUT OAD EST V DD nCLK V Cross Points PP CLK GND IFFERENTIAL NPUT EVEL Part 1 V ...

Page 9

IRING THE IFFERENTIAL NPUT TO Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V generated by the bias resistors R1, R2 and C1. This bias ...

Page 10

P C OWER ONSIDERATIONS For Power Dissipation, please refer to a separate Application Note: Power Dissipation for LVCMOS Buffer RIVER ERMINATION For LVCMOS Output Termination, please refer to a separate Application Note: LVCMOS Driver Termination. θ ...

Page 11

LQFP ACKAGE UTLINE UFFIX FOR ABLE θ ...

Page 12

ABLE RDERING NFORMATION ...

Page 13

...

Page 14

We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of ...

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