IDTMPC9448FA IDT, Integrated Device Technology Inc, IDTMPC9448FA Datasheet - Page 5
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IDTMPC9448FA
Manufacturer Part Number
IDTMPC9448FA
Description
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Driverr
Datasheet
1.IDTMPC9448FA.pdf
(12 pages)
Specifications of IDTMPC9448FA
Number Of Clock Inputs
2
Output Frequency
350MHz
Output Logic Level
LVCMOS
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.465V
Package Type
TQFP
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Signal Type
LVCMOS/LVPECL
Mounting
Surface Mount
Pin Count
32
Quiescent Current
2mA
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDTMPC9448FA
Manufacturer:
IDT
Quantity:
7 209
IDT™ 3.3 V/2.5 V LVCMOS 1:12 Clock Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
IDT™ / ICS™ LVCMOS 1:12 CLOCK FANOUT BUFFER
MPC9448
3.3 V/2.5 V LVCMOS 1:12 Clock Fanout Buffer
MPC9448
3.3V/2.5V LVCMOS 1:12 CLOCK FANOUT BUFFER
Table 8. AC Characteristics (V
1. AC characteristics apply for parallel output termination of 50 Ω to V
2. V
3. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input
4. Output pulse skew is the absolute difference of the propagation delay times: | t
Symbol
V
t
t
t
t
t
PLZ, HZ
t
PZL, LZ
and the input swing lies within the V
pulse width, output duty cycle and maximum frequency specifications.
PLH/HL
PLH/HL
P, REF
t
t
CMR
sk(PP)
DC
f
V
SK(p)
t
sk(O)
t
MAX
f
CMR
r
r
t
t
ref
, t
, t
PP
S
H
Q
f
f
(2)
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
Input Frequency
Maximum Output Frequency
Peak-to-peak input voltage
Common Mode Range
Reference Input Pulse Width
CCLK Input Rise/Fall Time
Propagation delay
Output Disable Time
Output Enable Time
Setup time
Hold time
Output-to-output Skew
Device-to-device Skew
Output pulse skew
Output Duty Cycle
Output Rise/Fall Time
(4)
CC
Characteristics
= 2.5 V ± 5%, T
PP
f
Q
f
(AC) specification. Violation of V
Q
< 350 MHz and using CCLK
<200 MHz and using PCLK
PCLK or CCLK to any Q
CCLK to CLK_STOP
CCLK to CLK_STOP
PCLK to CLK_STOP
PCLK to CLK_STOP
A
PCLK to any Q
CCLK to any Q
= -40°C to +85°C)
Using CCLK
Using PCLK
PCLK
PCLK
5
5
TT
.
CMR
Min
400
1.2
1.4
1.5
1.7
0.0
0.0
1.0
1.5
0.1
(1)
45
45
0
0
or V
pLH
PP
- t
impacts t
pHL
Typ
|.
50
50
PLH/HL
and t
V
CC
1.0
1000
Max
350
350
150
200
300
4.2
4.4
2.7
1.0
11
11
55
55
– 0.8
SK(PP)
(3)
MPC9448
.
Unit
MHz
MHz
mV
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ns
ps
ps
ns
%
%
V
LVPECL
LVPECL
0.8 to 2.0 V
DC
0.6 to 1.8 V
REV 6 JULY 11, 2006
REF
Condition
CMR
= 50%
NETCOM
range
MPC9448