ICS8530DY-01 IDT, Integrated Device Technology Inc, ICS8530DY-01 Datasheet - Page 9

• Manufacturer Part Number: ICS8530DY-01
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS8530DY-01

• Lead Free Status / RoHS Status: Supplier Unconfirmed

The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
designed to drive 50Ω transmission lines. Matched imped-
8530DY-01
T
RTT =
ERMINATION FOR
((V
FOUT
F
OH
IGURE
+ V
OL
Integrated
Circuit
Systems, Inc.
) / (V
3A. LVPECL O
1
LVPECL O
CC
Z
Z
– 2)) – 2
o
o
= 50Ω
= 50Ω
Z
o
50Ω
UTPUT
UTPUTS
T
ERMINATION
RTT
www.icst.com/products/hiperclocks.html
50Ω
V
CC
FIN
- 2V
D
IFFERENTIAL
9
ance techniques should be used to maximize operating
frequency and minimize signal distortion. Figures 3A and
3B show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
FOUT
-
F
TO
IGURE
-3.3V LVPECL F
3B. LVPECL O
Z
Z
o
o
= 50Ω
= 50Ω
125Ω
84Ω
L
UTPUT
OW
ICS8530-01
3.3V
S
T
125Ω
84Ω
ANOUT
ERMINATION
KEW
FIN
REV. E MAY 19, 2006
, 1-
B
TO
UFFER
-16