ICS8308AGI IDT, Integrated Device Technology Inc, ICS8308AGI Datasheet - Page 11

• Manufacturer Part Number: ICS8308AGI
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of ICS8308AGI

• Number Of Clock Inputs: 2
• Output Frequency: 350MHz
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / RoHS Status: Not Compliant

ICS8308I Data Sheet
F
F
ICS8308AGI REVISION C JULY 20, 2009
D
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
V
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
F
IGURE
PP
IGURE
IGURE
IFFERENTIAL
3.3V
and V
R5,R6 locate near the driver pin.
3.3V
LVPECL
2C. H
2A. H
2E. H
1.8V
CMR
LVPECL
R5
100 - 200
input requirements. Figures 2A to 2E show interface
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
3.3V LVPECL D
ICS H
3.3V LVPECL D
I
I
I
P
P
P
C
ER
ER
ER
Zo = 50 Ohm
Zo = 50 Ohm
LOCK
R6
100 - 200
C
Zo = 50 Ohm
Zo = 50 Ohm
C
C
I
P
Zo = 50 Ohm
Zo = 50 Ohm
LOCK
LOCK
LOCK
ER
C
I
NPUT
S CLK/nCLK I
S CLK/nCLK I
LOCK
S CLK/nCLK I
RIVER
S LVHSTL D
RIVER WITH
R1
50
3.3V
R3
125
C1
C2
I
R1
84
NTERFACE
3.3V
R3
125
R2
50
R4
125
SWING
R1
84
R2
84
R4
125
and V
CLK
nCLK
R2
84
NPUT
AC C
CLK
nCLK
NPUT
NPUT
3.3V
3.3V
HiPerClockS
Input
RIVER
OH
HiPerClockS
Input
D
D
D
OUPLE
CLK
nCLK
must meet the
RIVEN BY
RIVEN BY
RIVEN BY
3.3V
HiPerClockS
Input
11
LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in Figure 2A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
F
F
IGURE
IGURE
3.3V
3.3V
LVDS_Driv er
2D. H
2B. H
LVPECL
3.3V LVPECL D
3.3V LVDS D
I
I
P
P
Zo = 50 Ohm
Zo = 50 Ohm
ER
ER
C
C
LOCK
LOCK
Zo = 50 Ohm
Zo = 50 Ohm
S CLK/nCLK I
S CLK/nCLK I
RIVER
R1
50
R3
50
RIVER
2009 Integrated Device Technology, Inc.
R2
50
R1
100
CLK
nCLK
3.3V
NPUT
NPUT
HiPerClockS
Input
CLK
nCLK
D
D
3.3V
RIVEN BY
RIVEN BY
Receiv er