ICS85214AGI IDT, Integrated Device Technology Inc, ICS85214AGI Datasheet
ICS85214AGI
Specifications of ICS85214AGI
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ICS85214AGI Summary of contents
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G D ENERAL ESCRIPTION The ICS85214I is a low skew, high performance 1-to-5 Differential-to-HSTL The CLK0, nCLK0 pair can accept most standard differential input levels. The single ...
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ABLE IN ESCRIPTIONS ...
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T 3A ABLE ONTROL NPUT UNCTION ...
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BSOLUTE AXIMUM ATINGS Supply Voltage Inputs Outputs Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, T STG T 4A ABLE OWER UPPLY HARACTERISTICS S y ...
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T 4D. HSTL DC C ABLE HARACTERISTICS ...
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P ARAMETER 3.3V±5% 1.8V±0. DDO HSTL GND 0V 3.3V/1. UTPUT OAD EST nQx Qx nQy Qy t sk( UTPUT KEW CLK1 nQ0:nQ4 Q0: nCLK0 CLK0 nQ0:nQ4 Q0:Q4 t ...
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IRING THE IFFERENTIAL NPUT TO Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V generated by the bias resistors R1, R2 and C1. This bias ...
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IFFERENTIAL LOCK NPUT NTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V SWING V and V input requirements. Figures show PP CMR interface examples for the ...
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S E CHEMATIC XAMPLE Figure 4 shows a schematic example of the ICS85214I. In this example, the input is driven by an IDT HSTL driver. The decoupling capacitors should be physically located 1.8V R12 Ohm Zo = ...
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This section provides information on power dissipation and junction temperature for the ICS85214I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85214I is the sum of the core power plus the power ...
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Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 5. F IGURE T o calculate worst case power dissipation into the ...
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ABLE VS IR LOW ABLE FOR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains ...
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ACKAGE UTLINE UFFIX FOR T ABLE Reference Document: JEDEC Publication 95, MO-153 85214AGI D IFFERENTIAL TSSOP EAD ACKAGE IMENSIONS ...
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ABLE RDERING NFORMATION ...
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We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of ...