MT48LC4M32B2B5-7 IT:G Micron Technology Inc, MT48LC4M32B2B5-7 IT:G Datasheet - Page 33
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MT48LC4M32B2B5-7 IT:G
Manufacturer Part Number
MT48LC4M32B2B5-7 IT:G
Description
DRAM Chip SDRAM 128M-Bit 4Mx32 3.3V 90-Pin VFBGA Tray
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC4M32B2P-7G_TR.pdf
(67 pages)
Specifications of MT48LC4M32B2B5-7 IT:G
Density
128 Mb
Maximum Clock Rate
143 MHz
Package
90VFBGA
Address Bus Width
14 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
17|8|5.5 ns
Operating Temperature
-40 to 85 °C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
128M (4Mx32)
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
90-VFBGA
Organization
4Mx32
Address Bus
14b
Access Time (max)
17/8/5.5ns
Operating Supply Voltage (typ)
3.3V
Package Type
VFBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
175mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 24:
Clock Suspend
Figure 25:
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. L 1/09 EN
Power-Down
CLOCK SUSPEND During WRITE Burst
Notes:
COMMAND
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered low. In the clock suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input pins at the time of a
suspended internal clock edge is ignored; any data present on the DQ pins remains
driven; and burst counters are not incremented, as long as the clock is suspended. (See
examples in Figure 22 on page 31 and Figure 23 on page 32.)
Clock suspend mode is exited by registering CKE HIGH; the internal clock and related
operation will resume on the subsequent positive clock edge.
COMMAND
1. For this example, BL = 4 or greater, and DM is LOW.
CLK
CKE
INTERNAL
ADDRESS
CLOCK
All banks idle
Enter power-down mode.
CKE
CLK
D
IN
t CKS
NOP
T0
NOP
BANK,
WRITE
COL n
D
T1
n
IN
Input buffers gated off
T2
33
(
(
(
(
)
(
)
)
)
)
(
(
(
(
)
(
)
)
)
)
T3
Exit power-down mode.
NOP
n + 1
T4
D
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IN
> t CKS
DON’T CARE
T5
NOP
n + 2
D
NOP
IN
DON’T CARE
ACTIVE
t RCD
t RAS
t RC
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
Register Definition