MT48LC4M32B2B5-7 IT:G Micron Technology Inc, MT48LC4M32B2B5-7 IT:G Datasheet - Page 31

• Manufacturer Part Number: MT48LC4M32B2B5-7 IT:G
• Description: DRAM Chip SDRAM 128M-Bit 4Mx32 3.3V 90-Pin VFBGA Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC4M32B2B5-7 IT:G

• Density: 128 Mb
• Maximum Clock Rate: 143 MHz
• Package: 90VFBGA
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 17|8|5.5 ns
• Operating Temperature: -40 to 85 °C
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 128M (4Mx32)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 90-VFBGA
• Organization: 4Mx32
• Address Bus: 14b
• Access Time (max): 17/8/5.5ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 175mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 21:
Figure 22:
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. L 1/09 EN
WRITE-to-PRECHARGE
Terminating a WRITE Burst
Notes:
Notes:
COMMAND
COMMAND
1. DQM could remain LOW in this example if the WRITE burst is a fixed length of two.
Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE
command. When truncating a WRITE burst, the input data applied coincident with the
BURST TERMINATE command will be ignored. The last data written (provided that
DQM is LOW at that time) will be the input data applied one clock previous to the
BURST TERMINATE command. This is shown in Figure 22, where data n is the last
desired data element of a longer burst.
COMMAND
1. DQMs are LOW.
t
t
WR = 1 CLK (
WR = 2 CLK (when
ADDRESS
ADDRESS
ADDRESS
DQM
DQM
CLK
CLK
DQ
DQ
DQ
t
CK >
BANK a,
BANK a,
BANK,
WRITE
WRITE
WRITE
COL n
COL n
COL n
D
D
D
T0
T0
n
n
n
IN
IN
IN
t
t
WR)
WR >
TERMINATE
t
BURST
n + 1
n + 1
NOP
NOP
CK)
D
D
T1
T1
IN
IN
t
WR
DON’T CARE
PRECHARGE
COMMAND
(ADDRESS)
(a or all)
(DATA)
BANK
NOP
T2
T2
NEXT
t
31
WR
PRECHARGE
(a or all)
BANK
T3
NOP
t RP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
NOP
T4
t RP
BANK a,
ACTIVE
NOP
ROW
T5
DON’T CARE
BANK a,
ACTIVE
ROW
NOP
T6
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
Register Definition