MT48LC4M32B2B5-7 IT:G Micron Technology Inc, MT48LC4M32B2B5-7 IT:G Datasheet - Page 18

• Manufacturer Part Number: MT48LC4M32B2B5-7 IT:G
• Description: DRAM Chip SDRAM 128M-Bit 4Mx32 3.3V 90-Pin VFBGA Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC4M32B2B5-7 IT:G

• Density: 128 Mb
• Maximum Clock Rate: 143 MHz
• Package: 90VFBGA
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 17|8|5.5 ns
• Operating Temperature: -40 to 85 °C
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 128M (4Mx32)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 90-VFBGA
• Organization: 4Mx32
• Address Bus: 14b
• Access Time (max): 17/8/5.5ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 175mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LOAD MODE REGISTER
ACTIVE
READ
WRITE
PRECHARGE
Auto Precharge
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. L 1/09 EN
The mode register is loaded via inputs A0–A11. See the Mode Register heading in the
“Register Definition” section. The LOAD MODE REGISTER command can only be issued
when all banks are idle, and a subsequent executable command cannot be issued until
t
The ACTIVE command is used to open (or activate) a row in a particular bank for a
subsequent access. The value on the BA0 and BA1 inputs selects the bank, and the
address provided on inputs A0–A11 selects the row. This row remains active (or open) for
accesses until a precharge command is issued to that bank. A precharge command must
be issued before opening a different row in the same bank.
The READ command is used to initiate a burst read access to an active row. The value on
the BA0 and BA1 (B1) inputs selects the bank, and the address provided on inputs A0–A7
selects the starting column location. The value on input A10 determines whether or not
auto precharge is used. If auto precharge is selected, the row being accessed will be
precharged at the end of the read burst; if auto precharge is not selected, the row will
remain open for subsequent accesses. Read data appears on the DQs subject to the logic
level on the DQM inputs two clocks earlier. If a given DQMx signal was registered HIGH,
the corresponding DQs will be High-Z two clocks later; if the DQMx signal was registered
LOW, the corresponding DQs will provide valid data. DQM0 corresponds to DQ0–DQ7,
DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–DQ23 and DQM3
corresponds to DQ24–DQ31.
The WRITE command is used to initiate a burst write access to an active row. The value
on the BA0 and BA1 inputs selects the bank, and the address provided on inputs A0–A7
selects the starting column location. The value on input A10 determines whether or not
auto precharge is used. If auto precharge is selected, the row being accessed will be
precharged at the end of the write burst; if auto precharge is not selected, the row will
remain open for subsequent accesses. Input data appearing on the DQs is written to the
memory array subject to the DQM input logic level appearing coincident with the data.
If a given DQM signal is registered LOW, the corresponding data will be written to
memory; if the DQM signal is registered HIGH, the corresponding data inputs will be
ignored, and a write will not be executed to that byte/column location.
the open row in all banks. The bank(s) will be available for a subsequent row access a
specified time (
whether one or all banks are to be precharged, and in the case where only one bank is to
be precharged, inputs BA0 and BA1 select the bank. Otherwise BA0 and BA1 are treated
as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be acti-
vated prior to any READ or WRITE commands being issued to that bank.
Auto precharge is a feature which performs the same individual-bank precharge func-
tion described above, without requiring an explicit command. This is accomplished by
using A10 to enable auto precharge in conjunction with a specific READ or WRITE
The PRECHARGE command is used to deactivate the open row in a particular bank or
MRD is met.
t
RP) after the precharge command is issued. Input A10 determines
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
Register Definition