MT47H128M8CF-3:H Micron Technology Inc, MT47H128M8CF-3:H Datasheet - Page 88

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MT47H128M8CF-3:H

Manufacturer Part Number
MT47H128M8CF-3:H
Description
DRAM Chip DDR2 SDRAM 1G-Bit 128Mx8 1.8V 60-Pin FBGA Tray
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Series
-r
Datasheet

Specifications of MT47H128M8CF-3:H

Density
1 Gb
Maximum Clock Rate
667 MHz
Package
60FBGA
Address Bus Width
17 Bit
Operating Supply Voltage
1.8 V
Maximum Random Access Time
0.45 ns
Operating Temperature
0 to 85 °C
Organization
128Mx8
Address Bus
17b
Access Time (max)
450ps
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
0C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
115mA
Pin Count
60
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
1G (128M x 8)
Speed
3ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Package / Case
60-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Initialization
Figure 42: DDR2 Power-Up and Initialization
DDR2 SDRAM must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in unde-
fined operation. Figure 42 illustrates, and the notes outline, the sequence required for power-up and initialization.
Command
Address
DQS
DM
DQ
V
V
V
ODT
V
V
CK#
CKE
DDQ
DDL
R
TT
CK
REF
DD
15
16
15
15
tt
1
low level 2
LVCMOS
High-Z
High-Z
High-Z
t
VTD 1
T0
t CL
V
clock (CK, CK#)
low level
T = 200µs (MIN) 3
Power-up:
SSTL_18
DD
t CK
and stable
t CL
2
NOP 3
Ta0
T = 400ns (MIN) 4
A10 = 1
Tb0
PRE
t RPA
EMR(2)
LM 5
Code
Tc0
t MRD
EMR(3)
Code
LM 6
Td0
t MRD
Code
LM 7
EMR
Te0
t MRD
DLL RESET
MR with
Code
LM 8
Tf0
t MRD
A10 = 1
PRE 9
Tg0
t RPA
200 cycles of CK are required before a READ command can be issued
REF 10
Th0
t RFC
See no te 10
REF 10
Ti0
t RFC
MR without
DLL RESET
LM 11
Code
Tj0
t MRD
OCD default
EMR with
LM 12
Code
Tk0
Indicates a Break in
Time Scale
t MRD
EMR with
OCD exit
LM 13
Code
Tl0
t MRD
operation
Don’t care
Normal
Valid 14
Valid
Tm0

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