MT47H128M8CF-3:H Micron Technology Inc, MT47H128M8CF-3:H Datasheet - Page 127

• Manufacturer Part Number: MT47H128M8CF-3:H
• Description: DRAM Chip DDR2 SDRAM 1G-Bit 128Mx8 1.8V 60-Pin FBGA Tray
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr
• Series: -r

Specifications of MT47H128M8CF-3:H

• Density: 1 Gb
• Maximum Clock Rate: 667 MHz
• Package: 60FBGA
• Address Bus Width: 17 Bit
• Operating Supply Voltage: 1.8 V
• Maximum Random Access Time: 0.45 ns
• Operating Temperature: 0 to 85 °C
• Organization: 128Mx8
• Address Bus: 17b
• Access Time (max): 450ps
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 115mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 1G (128M x 8)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Package / Case: 60-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 79: RESET Function
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. V 6/10 EN
Bank address
Command
Address
ODT
DQS 3
DM 3
CK#
CKE
A10
DQ 3
R
CK
TT
Bank a
READ
Col n
T0
High-Z
High-Z
Notes:
NOP 2
T1
1. V
2. Either NOP or DESELECT command may be applied.
3. DM represents DM for x4/x8 configuration and UDM, LDM for x16 configuration. DQS
4. In certain cases where a READ cycle is interrupted, CKE going HIGH may result in the
5. Initialization timing is shown in Figure 42 (page 88).
represents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, and RDQS# for the appropri-
ate configuration (x4, x8, x16).
completion of the burst.
DD
Bank b
Col n
READ
, V
T2
DDL
, V
DDQ
NOP 2
Indicates a break in
time scale
T3
, V
DO
TT
, and V
DO
NOP 2
T4
127
System
DO
RESET
REF
must be valid at all times.
t DELAY
Unknown
T5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1
1Gb: x4, x8, x16 DDR2 SDRAM
R
TT
On
High-Z
High-Z
Transitioning Data
t CL
© 2004 Micron Technology, Inc. All rights reserved.
t CK
Start of normal 5
initialization
t CL
sequence
NOP 2
Ta0
4
T = 400ns (MIN)
t CKE (MIN)
All banks
Tb0
PRE
Don’t Care
High-Z
t RPA
Reset