TDA8295HN/C1 NXP Semiconductors, TDA8295HN/C1 Datasheet - Page 47

• Manufacturer Part Number: TDA8295HN/C1
• Description: Modulator / Demodulator IF DEMODULATOR
• Manufacturer: NXP Semiconductors

Specifications of TDA8295HN/C1

• Package / Case: HVQFN-40
• Maximum Operating Temperature: + 70 C
• Maximum Power Dissipation: 490 mW
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.2 V, 3.3 V
• Supply Current: 0.136 A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: TDA8295HN/C1,557

NXP Semiconductors
TDA8295_1
Product data sheet
Table 58.
Legend: * = default value.
Table 59.
Legend: * = default value.
[1]
For optimum performances, the following relations must be respected:
Bit
7
6
5
4
3
2 and 1 -
0
DIRECTI
1
1
0
0*
•
•
For description of M, N and P see
275 MHz
4 kHz
Symbol
-
CLK_EN
BYP_PLL
DIRECTO
DIRECTI
PD_PLL
PLL_REG06 register (address 3Eh) bit description
Truth table for PLL output clock frequency
f
i
Digital global standard low IF demodulator for analog TV and FM radio
f
150 MHz if DIRECTI = 1, else 4 kHz
VCO
DIRECTO
1
0
1
0*
Rev. 01 — 4 February 2008
550 MHz
Access Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table
0
0
1*
X
0
1*
X
0*
0*
00
0
1*
X
60.
PLL output clock frequency
f
clk(o)(PLL)
f
f
f
clk(o)(PLL)
clk(o)(PLL)
clk(o)(PLL)
Description
reserved, must be set to logic 0
CLK_EN controls the PLL output clock
When HIGH, the internal clocks (for logic, ADC, and
DACs) are directly controlled by the pin XIN.
BYP_PLL acts both on external multiplexers and on
internal PLL bypass. When PLL initialization is
automatic (PLL_AUTO = 1), BYP_PLL is not
considered.
When DIRECTI is set to logic 1, the pre-divider is
bypassed. If DIRECTO is equal to logic 1, then it is
the post-divider, which is bypassed. Please see
Table 59
reserved, must be set to logic 00
Put the PLL in Power-down mode if equal to logic 1.
When PLL initialization is automatic
(PLL_AUTO = 1), PD_PLL is not considered.
PLL output clock disable
PLL output clock enable
don’t care if PLL_AUTO = 1
internal clocks are controlled by PLL clock
internal clocks are controlled by pin XIN
don’t care if PLL_AUTO = 1
PLL active
PLL Power-down mode
don’t care if PLL_AUTO = 1
= f
=
=
=
VCO
for further details.
------------ -
------------ -
2 P
2 P
f
f
f
VCO
VCO
VCO
= f
f
i
i
/ N
=
=
=
2
-------------------------
--------------- -
--------------- -
f
f
f
N
i
i
i
P
150 MHz
M
N
2
M
M
P
[1]
M
TDA8295
© NXP B.V. 2008. All rights reserved.
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