PBLS2002S,115 NXP Semiconductors, PBLS2002S,115 Datasheet

LOADSWITCH PNP 20V 3A 8-SOIC

PBLS2002S,115

Manufacturer Part Number
PBLS2002S,115
Description
LOADSWITCH PNP 20V 3A 8-SOIC
Manufacturer
NXP Semiconductors
Series
-r
Datasheet

Specifications of PBLS2002S,115

Package / Case
8-SOIC (3.9mm Width)
Transistor Type
1 NPN Pre-Biased, 1 PNP
Current - Collector (ic) (max)
100mA, 3A
Voltage - Collector Emitter Breakdown (max)
50V, 20V
Resistor - Base (r1) (ohms)
4.7K
Resistor - Emitter Base (r2) (ohms)
4.7K
Dc Current Gain (hfe) (min) @ Ic, Vce
30 @ 10mA, 5V / 150 @ 2A, 2V
Vce Saturation (max) @ Ib, Ic
150mV @ 500µA, 10mA / 355mV @ 300mA, 3A
Current - Collector Cutoff (max)
1µA, 100nA
Frequency - Transition
100MHz
Power - Max
1.5W
Mounting Type
Surface Mount
Configuration
Dual Dual Collector
Transistor Polarity
NPN/PNP
Typical Input Resistor
4.7 KOhms at NPN
Typical Resistor Ratio
1 at NPN
Mounting Style
SMD/SMT
Collector- Emitter Voltage Vceo Max
50 V at NPN, 20 V at PNP
Peak Dc Collector Current
100 mA at NPN, 3000 mA at PNP
Maximum Operating Temperature
+ 150 C
Minimum Operating Temperature
- 65 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
934060278115
PBLS2002S T/R
PBLS2002S T/R
1. Product profile
1.1 General description
1.2 Features
1.3 Applications
1.4 Quick reference data
PNP low V
Equipped Transistor (RET) in a SOT96-1 (SO8) small Surface-Mounted Device (SMD)
plastic package.
I
I
I
I
I
I
I
I
I
Table 1.
[1]
Symbol
TR1; PNP low V
V
I
R
TR2; NPN resistor-equipped transistor
V
I
R1
R2/R1
C
O
CEO
CEO
CEsat
PBLS2002S
20 V PNP BISS loadswitch
Rev. 02 — 24 August 2009
Low V
Low threshold voltage (< 1 V) compared to MOSFET
Low drive power required
Space-saving solution
Reduction of component count
Supply line switches
Battery charger switches
High-side switches for LEDs, drivers and backlights
Portable equipment
Pulse test: t
CEsat
CEsat
Quick reference data
Parameter
collector-emitter voltage
collector current
collector-emitter saturation
resistance
collector-emitter voltage
output current
bias resistor 1 (input)
bias resistor ratio
p
(BISS) transistor and resistor-equipped transistor in one package
CEsat
Breakthrough In Small Signal (BISS) transistor and NPN Resistor-
300 s;
(BISS) transistor
0.02
Conditions
open base
I
I
open base
C
B
= 200 mA
= 2 A;
[1]
Min
-
-
-
-
-
3.3
0.8
Typ
-
-
75
-
-
4.7
1
Product data sheet
Max
120
50
100
6.1
1.2
20
3
Unit
V
A
m
V
mA
k

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PBLS2002S,115 Summary of contents

Page 1

PBLS2002S 20 V PNP BISS loadswitch Rev. 02 — 24 August 2009 1. Product profile 1.1 General description PNP low V Equipped Transistor (RET SOT96-1 (SO8) small Surface-Mounted Device (SMD) plastic package. 1.2 Features I Low V I ...

Page 2

... NXP Semiconductors 2. Pinning information Table 2. Pin Ordering information Table 3. Type number PBLS2002S 4. Marking Table 4. Type number PBLS2002S PBLS2002S_2 Product data sheet Pinning Description input (base) TR2 GND (emitter) TR2 base TR1 emitter TR1 collector TR1 collector TR1 output (collector) TR2 output (collector) TR2 ...

Page 3

... NXP Semiconductors 5. Limiting values Table 5. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol TR1; PNP low V V CBO V CEO V EBO tot TR2; NPN resistor-equipped transistor V CBO V CEO V EBO tot Per device P tot amb T stg [1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint ...

Page 4

... NXP Semiconductors (1) Ceramic PCB, Al (2) FR4 PCB, mounting pad for collector 1cm (3) FR4 PCB, standard footprint Fig 1. 6. Thermal characteristics Table 6. Symbol Per device R th(j-a) TR1; PNP low V R th(j-sp) [1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. ...

Page 5

... NXP Semiconductors 3 10 duty cycle = Z th(j-a) (K/W) 1.0 0. 0.5 0.33 0.2 0.1 0.05 10 0.02 0. FR4 PCB, standard footprint Fig 2. TR1 (PNP): Transient thermal impedance from junction to ambient as a function of pulse duration; typical values 3 10 duty cycle = Z th(j-a) (K/W) 1 0.75 0.5 0.33 ...

Page 6

... NXP Semiconductors th(j-a) (K/W) duty cycle = 2 10 1.0 0.75 0.5 0.33 0.2 10 0.1 0.05 0.02 0. Ceramic PCB standard footprint 2 3 Fig 4. TR1 (PNP): Transient thermal impedance from junction to ambient as a function of pulse duration; typical values 7. Characteristics Table unless otherwise specified ...

Page 7

... NXP Semiconductors Table unless otherwise specified amb Symbol V BEsat V BEon off TR2; NPN resistor-equipped transistor I CBO I CEO I EBO CEsat V I(off) V I(on) R1 R2/ [1] Pulse test: t PBLS2002S_2 Product data sheet Characteristics …continued Parameter Conditions base-emitter saturation voltage base-emitter turn- voltage delay time ...

Page 8

... NXP Semiconductors 800 h FE (1) 600 (2) 400 (3) 200 ( 100 C amb ( amb ( amb Fig 5. TR1 (PNP): DC current gain as a function of collector current; typical values 1 (V) 0.9 (1) 0.7 (2) 0.5 (3) 0 amb ( amb ( 100 C amb Fig 7. TR1 (PNP): Base-emitter voltage as a function of collector current; typical values ...

Page 9

... NXP Semiconductors 1 V CEsat (V) ( 100 C amb ( amb ( amb Fig 9. TR1 (PNP): Collector-emitter saturation voltage as a function of collector current; typical values 10 R CEsat ( ) ( 100 C amb ( amb ( amb Fig 11. TR1 (PNP): Collector-emitter saturation resistance as a function of collector current; typical values PBLS2002S_2 Product data sheet ...

Page 10

... NXP Semiconductors ( 150 C amb ( amb ( amb Fig 13. TR2 (NPN): DC current gain as a function of collector current; typical values 10 V I(on) (V) (1) ( amb ( amb ( 100 C amb Fig 15. TR2 (NPN): On-state input voltage as a function of collector current; typical values PBLS2002S_2 Product data sheet ...

Page 11

... NXP Semiconductors 8. Test information Fig 17. BISS transistor switching time definition Fig 18. Test circuit for switching times PBLS2002S_2 Product data sheet (probe) oscilloscope 450 100 mA 100 mA open Bon Boff Rev. 02 — 24 August 2009 PBLS2002S 20 V PNP BISS loadswitch input pulse (idealized waveform) ...

Page 12

... NXP Semiconductors 9. Package outline Fig 19. Package outline SOT96-1 (SO8) 10. Packing information Table 8. The indicated -xxx are the last three digits of the 12NC ordering code. Type number PBLS2002S [1] For further information and the availability of packing methods, see PBLS2002S_2 Product data sheet 5.0 4 ...

Page 13

... NXP Semiconductors 11. Soldering Fig 20. Reflow soldering footprint SOT96-1 (SO8) Fig 21. Wave soldering footprint SOT96-1 (SO8) PBLS2002S_2 Product data sheet 5.50 0. solder lands occupied area placement accuracy 5.50 board direction solder lands solder resist placement accurracy 0.25 occupied area Rev. 02 — ...

Page 14

... Revision history Document ID Release date PBLS2002S_2 20090824 • Modifications: This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content. PBLS2002S_1 20060804 PBLS2002S_2 Product data sheet ...

Page 15

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 16

... NXP Semiconductors 15. Contents 1 Product profi 1.1 General description 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.4 Quick reference data Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Limiting values Thermal characteristics Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 Test information . . . . . . . . . . . . . . . . . . . . . . . . 11 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 10 Packing information Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 12 Revision history ...

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