XC3S1500-4FGG676C Xilinx Inc, XC3S1500-4FGG676C Datasheet - Page 87

• Manufacturer Part Number: XC3S1500-4FGG676C
• Description: FPGA Spartan®-3 Family 1.5M Gates 29952 Cells 630MHz 90nm Technology 1.2V 676-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S1500-4FGG676C

• Package: 676FBGA
• Family Name: Spartan®-3
• Device Logic Units: 29952
• Device System Gates: 1500000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 487
• Ram Bits: 589824
• Number Of Logic Elements/cells: 29952
• Number Of Labs/clbs: 3328
• Total Ram Bits: 589824
• Number Of I /o: 487
• Number Of Gates: 1500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 676-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: NANO-SPARTAN - KIT NANOBOARD AND SPARTAN3 DC807-1001 - DAUGHTER CARD XILINX SPARTAN 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1337

Table 58: Switching Characteristics for the DLL
DS099-3 (v2.5) December 4, 2009
Product Specification
98
Output Frequency Ranges
CLKOUT_FREQ_1X_LF
CLKOUT_FREQ_1X_HF
CLKOUT_FREQ_2X_LF
CLKOUT_FREQ_DV_LF
CLKOUT_FREQ_DV_HF
Output Clock Jitter
CLKOUT_PER_JITT_0
CLKOUT_PER_JITT_90
CLKOUT_PER_JITT_180
CLKOUT_PER_JITT_270
CLKOUT_PER_JITT_2X
CLKOUT_PER_JITT_DV1
CLKOUT_PER_JITT_DV2
Duty Cycle
CLKOUT_DUTY_CYCLE_DLL
Phase Alignment
CLKIN_CLKFB_PHASE
CLKOUT_PHASE
Symbol
R
(4)
(3)
(5)
Frequency for the CLK0,
CLK90, CLK180, and CLK270
outputs
Frequency for the CLK0 and
CLK180 outputs
Frequency for the CLK2X and
CLK2X180 outputs
Frequency for the CLKDV
output
Period jitter at the CLK0 output
Period jitter at the CLK90 output
Period jitter at the CLK180
output
Period jitter at the CLK270
output
Period jitter at the CLK2X and
CLK2X180 outputs
Period jitter at the CLKDV
output when performing integer
division
Period jitter at the CLKDV
output when performing
non-integer division
Duty cycle variation for the
CLK0, CLK90, CLK180,
CLK270, CLK2X, CLK2X180,
and CLKDV outputs
Phase offset between the
CLKIN and CLKFB inputs
Phase offset between any two
DLL outputs (except CLK2X
and CLK0)
Phase offset between the
CLK2X and CLK0 outputs
Description
Spartan-3 FPGA Family: DC and Switching Characteristics
www.xilinx.com
Frequency Mode /
F
CLKIN
High
High
Low
Low
Low
All
All
All
Range
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
Device
All
All
All
1.125
Min
18
48
36
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-5
Speed Grade
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
Max
167
280
334
110
185
100
150
150
150
200
150
300
150
150
250
400
400
400
400
400
150
140
250
1.125
Min
18
48
36
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-4
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
Max
167
280
334
110
185
100
150
150
150
200
150
300
150
150
250
400
400
400
400
400
150
140
250
Units
MHz
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
87