XC3S1500-4FGG676C Xilinx Inc, XC3S1500-4FGG676C Datasheet - Page 85
![FPGA Spartan®-3 Family 1.5M Gates 29952 Cells 630MHz 90nm Technology 1.2V 676-Pin FBGA](/photos/6/73/67300/b-676_sml.jpg)
XC3S1500-4FGG676C
Manufacturer Part Number
XC3S1500-4FGG676C
Description
FPGA Spartan®-3 Family 1.5M Gates 29952 Cells 630MHz 90nm Technology 1.2V 676-Pin FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3r
Datasheet
1.XC3S50-4VQG100C.pdf
(217 pages)
Specifications of XC3S1500-4FGG676C
Package
676FBGA
Family Name
Spartan®-3
Device Logic Units
29952
Device System Gates
1500000
Maximum Internal Frequency
630 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
487
Ram Bits
589824
Number Of Logic Elements/cells
29952
Number Of Labs/clbs
3328
Total Ram Bits
589824
Number Of I /o
487
Number Of Gates
1500000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
NANO-SPARTAN - KIT NANOBOARD AND SPARTAN3 DC807-1001 - DAUGHTER CARD XILINX SPARTAN 3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1337
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Table 55: Block RAM Timing
Clock Distribution Switching Characteristics
Table 56: Clock Distribution Switching Characteristics
DS099-3 (v2.5) December 4, 2009
Product Specification
98
Notes:
1.
2.
Notes:
1.
Clock-to-Output Times
T
Setup Times
T
Hold Times
T
Clock Timing
T
T
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I-input to O-output delay
Global clock multiplexer (BUFGMUX) select S-input setup to I0- and
I1-inputs. Same as BUFGCE enable CE-input
BCKO
BDCK
BCKD
BPWH
BPWL
The numbers in this table are based on the operating conditions set forth in
For minimums, use the values reported by the Xilinx timing analyzer.
For minimums, use the values reported by the Xilinx timing analyzer.
Symbol
R
When reading from the Block
RAM, the time from the active
transition at the CLK input to
data appearing at the DOUT
output
Time from the setup of data at
the DIN inputs to the active
transition at the CLK input of the
Block RAM
Time from the active transition
at the Block RAM’s CLK input to
the point where data is last held
at the DIN inputs
Block RAM CLK signal High
pulse width
Block RAM CLK signal Low
pulse width
Description
Description
Spartan-3 FPGA Family: DC and Switching Characteristics
www.xilinx.com
0.43
1.19
1.19
Min
0
-
-5
Max
2.09
Table
∞
∞
-
-
Speed Grade
31.
Symbol
T
T
GIO
GSI
0.49
1.37
1.37
Min
0
-
0.36
0.53
-4
Speed Grade
-5
Maximum
Max
2.40
∞
∞
-
-
0.41
0.60
-4
Units
ns
ns
ns
ns
ns
Units
ns
ns
85