XC3S1500-4FGG676C Xilinx Inc, XC3S1500-4FGG676C Datasheet - Page 13
![FPGA Spartan®-3 Family 1.5M Gates 29952 Cells 630MHz 90nm Technology 1.2V 676-Pin FBGA](/photos/6/73/67300/b-676_sml.jpg)
XC3S1500-4FGG676C
Manufacturer Part Number
XC3S1500-4FGG676C
Description
FPGA Spartan®-3 Family 1.5M Gates 29952 Cells 630MHz 90nm Technology 1.2V 676-Pin FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3r
Datasheet
1.XC3S50-4VQG100C.pdf
(217 pages)
Specifications of XC3S1500-4FGG676C
Package
676FBGA
Family Name
Spartan®-3
Device Logic Units
29952
Device System Gates
1500000
Maximum Internal Frequency
630 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
487
Ram Bits
589824
Number Of Logic Elements/cells
29952
Number Of Labs/clbs
3328
Total Ram Bits
589824
Number Of I /o
487
Number Of Gates
1500000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
NANO-SPARTAN - KIT NANOBOARD AND SPARTAN3 DC807-1001 - DAUGHTER CARD XILINX SPARTAN 3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1337
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S1500-4FGG676C
Manufacturer:
XILINX
Quantity:
7
Company:
Part Number:
XC3S1500-4FGG676C
Manufacturer:
XILINX
Quantity:
350
Company:
Part Number:
XC3S1500-4FGG676C
Manufacturer:
XilinxInc
Quantity:
3 000
Company:
Part Number:
XC3S1500-4FGG676C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S1500-4FGG676C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
DS099-2 (v2.5) December 4, 2009
Product Specification
OTCLK1
OTCLK2
ICLK1
ICLK2
TCE
OCE
REV
ICE
IQ1
IQ2
T1
T2
SR
O1
O2
T
I
R
Note: All IOB signals originating from the FPGA's internal logic have an optional polarity inverter.
D
CE
CK
D
CE
CK
D
CE
CK
D
CE
CK
D
CE
CK
D
CE
CK
SR
SR
SR
SR
SR
SR
REV
REV
REV
REV
REV
REV
Q
Q
Q
Q
Q
Q
Figure 5: Simplified IOB Diagram
TFF1
TFF2
OFF1
OFF2
IFF1
IFF2
MUX
DDR
DDR
MUX
www.xilinx.com
Delay
Fixed
Delay
Fixed
Three-state Path
Output Path
Input Path
Spartan-3 FPGA Family: Functional Description
Program-
Output
mable
Driver
Single-ended Standards
LVCMOS, LVTTL, PCI
Differential Standards
using V REF
DCI
Pull-Up
Down
Pull-
Keeper
Latch
DS099-2_01_112905
ESD
ESD
V
Pin
I/O Pin
from
Adjacent
IOB
V
CCO
REF
I/O
Pin
13