XC2VP20-6FG676I Xilinx Inc, XC2VP20-6FG676I Datasheet - Page 84

• Manufacturer Part Number: XC2VP20-6FG676I
• Description: FPGA Virtex-II Pro™ Family 20880 Cells 1200MHz 0.13um/90nm (CMOS) Technology 1.5V 676-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-II Pror

Specifications of XC2VP20-6FG676I

• Package: 676FBGA
• Family Name: Virtex-II Pro™
• Device Logic Units: 20880
• Number Of Registers: 18560
• Maximum Internal Frequency: 1200 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 404
• Ram Bits: 1622016
• Number Of Logic Elements/cells: 20880
• Number Of Labs/clbs: 2320
• Total Ram Bits: 1622016
• Number Of I /o: 404
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 676-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 19: Processor Block JTAG Switching Characteristics
Table 20: PowerPC 405 Data-Side On-Chip Memory Switching Characteristics
Table 21: PowerPC 405 Instruction-Side On-Chip Memory Switching Characteristics
DS083 (v4.7) November 5, 2007
Product Specification
Setup and Hold Relative to Clock (JTAGC405TCK)
Clock to Out
Setup and Hold Relative to Clock
(BRAMDSOCMCLK)
Clock to Out
Setup and Hold Relative to Clock (BRAMISOCMCLK)
Clock to Out
JTAG control inputs
JTAG reset input
JTAG control outputs
Data-Side On-Chip Memory data bus inputs
Data-Side On-Chip Memory control outputs
Data-Side On-Chip Memory address bus outputs
Data-Side On-Chip Memory data bus outputs
Instruction-Side On-Chip Memory data bus inputs
Instruction-Side On-Chip Memory control outputs
Instruction-Side On-Chip Memory address bus outputs
Instruction-Side On-Chip Memory data bus outputs
R
Description
Description
Description
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
www.xilinx.com
T
T
T
T
T
T
T
T
T
T
T
PCCK
T
PCKC
PCKCO
PCKDO
T
PCKAO
T
PDCK
PCKCO
PCKDO
PCKAO
T
PCKD
PDCK
PCKD
PCKCO
PCCK
PCKC
Symbol
Symbol
Symbol
_JTAGRST/
_JTAGRST
_DSOCM/
_DSOCM
_ISOCM/
_ISOCM
_DSOCM
_DSOCM
_DSOCM
_JTAG/
_ISOCM
_ISOCM
_ISOCM
_JTAG
_JTAG
0.80/ 0.70
0.80/ 0.70
0.73/ 0.83
0.81/ 0.68
1.34
1.58
1.46
0.90
1.33
1.52
1.35
-7
-7
-7
Speed Grade
Speed Grade
Speed Grade
0.80/ 0.70
0.80/ 0.70
0.84/ 0.95
0.93/ 0.78
1.54
1.82
1.68
1.03
1.53
1.75
1.55
-6
-6
-6
0.88/ 0.77
0.88/ 0.77
0.92/ 1.05
1.02/ 0.86
1.69
1.99
1.84
1.13
1.68
1.92
1.70
-5
-5
-5
Module 3 of 4
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, min
ns, min
ns, min
ns, min
Units
Units
Units
13