XC2VP20-6FG676I Xilinx Inc, XC2VP20-6FG676I Datasheet - Page 66

• Manufacturer Part Number: XC2VP20-6FG676I
• Description: FPGA Virtex-II Pro™ Family 20880 Cells 1200MHz 0.13um/90nm (CMOS) Technology 1.5V 676-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-II Pror

Specifications of XC2VP20-6FG676I

• Package: 676FBGA
• Family Name: Virtex-II Pro™
• Device Logic Units: 20880
• Number Of Registers: 18560
• Maximum Internal Frequency: 1200 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 404
• Ram Bits: 1622016
• Number Of Logic Elements/cells: 20880
• Number Of Labs/clbs: 2320
• Total Ram Bits: 1622016
• Number Of I /o: 404
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 676-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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Dedicated Routing
In addition to the global and local routing resources, dedi-
cated signals are available.
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DS083 (v4.7) November 5, 2007
Product Specification
The double lines route signals to every first or second
block away in all four directions. Organized in a
staggered pattern, double lines can be driven only at
their endpoints. Double-line signals can be accessed
either at the endpoints or at the midpoint (one block
from the source).
The direct connect lines route signals to neighboring
blocks: vertically, horizontally, and diagonally.
The fast connect lines are the internal CLB local
interconnections from LUT outputs to LUT inputs.
There are eight global clock nets per quadrant. (See
Global Clock Multiplexer Buffers, page
R
48.)
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
www.xilinx.com
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Horizontal routing resources are provided for on-chip
3-state buses. Four partitionable bus lines are provided
per CLB row, permitting multiple buses within a row.
(See
Two dedicated carry-chain resources per slice column
(two per CLB column) propagate carry-chain MUXCY
output signals vertically to the adjacent slice. (See
CLB/Slice Configurations, page
One dedicated SOP chain per slice row (two per CLB
row) propagate ORCY output logic signals horizontally
to the adjacent slice. (See
One dedicated shift-chain per CLB connects the output
of LUTs in shift-register mode to the input of the next
LUT in shift-register mode (vertically) inside the CLB.
(See
3-State Buffers, page
Shift Registers, page
Sum of Products, page
43.)
39.)
44.)
Module 2 of 4
42.)
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