XA3S500E-4PQG208Q Xilinx Inc, XA3S500E-4PQG208Q Datasheet - Page 7

• Manufacturer Part Number: XA3S500E-4PQG208Q
• Description: FPGA XA Spartan™-3E Family 500K Gates 10476 Cells 572MHz 90nm Technology 1.2V 208-Pin PQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3E XAr

Specifications of XA3S500E-4PQG208Q

• Package: 208PQFP
• Family Name: XA Spartan™-3E
• Device Logic Units: 10476
• Device System Gates: 500000
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 158
• Ram Bits: 368640
• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Total Ram Bits: 368640
• Number Of I /o: 158
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Power Supply Specifications
Table 3: Supply Voltage Thresholds for Power-On Reset
Table 4: Supply Voltage Ramp Rate
Table 5: Supply Voltage Levels Necessary for Preserving RAM Contents
DS635 (v2.0) September 9, 2009
Product Specification
Notes:
1.
2.
Notes:
1.
2.
Notes:
1.
V
NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration source.
To ensure successful power-on, V
no dips at any point.
V
NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration source.
To ensure successful power-on, V
no dips at any point.
Symbol
RAM contents include configuration data.
V
V
CCINT
CCINT
DRAUX
V
V
DRINT
V
Symbol
V
Symbol
V
V
CCAUXR
CCAUXT
CCINTR
CCINTT
CCO2R
CCO2T
, V
, V
R
CCAUX
CCAUX
, and V
, and V
V
V
CCINT
CCAUX
Threshold for the V
Threshold for the V
Threshold for the V
Ramp rate from GND to valid V
Ramp rate from GND to valid V
Ramp rate from GND to valid V
CCO
CCO
level required to retain RAM data
level required to retain RAM data
supplies to the FPGA can be applied in any order. However, the FPGA’s configuration source (SPI Flash, parallel
supplies to the FPGA can be applied in any order. However, the FPGA’s configuration source (SPI Flash, parallel
CCINT
CCINT
, V
, V
CCO
CCO
CCINT
CCAUX
CCO
Bank 2, and V
Bank 2, and V
Description
Description
Bank 2 supply
supply
supply
Description
CCINT
CCAUX
CCO
www.xilinx.com
CCAUX
CCAUX
Bank 2 supply level
supply level
supplies must rise through their respective threshold-voltage ranges with
supplies must rise through their respective threshold-voltage ranges with
supply level
Min
Min
0.4
0.8
0.4
0.2
0.2
0.2
Max
Max
1.0
2.0
1.0
50
50
50
Min
1.0
2.0
Units
Units
Units
ms
ms
ms
V
V
V
V
V
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