XA3S500E-4PQG208Q Xilinx Inc, XA3S500E-4PQG208Q Datasheet - Page 25
![FPGA XA Spartan™-3E Family 500K Gates 10476 Cells 572MHz 90nm Technology 1.2V 208-Pin PQFP](/photos/6/71/67100/pq208_sml.jpg)
XA3S500E-4PQG208Q
Manufacturer Part Number
XA3S500E-4PQG208Q
Description
FPGA XA Spartan™-3E Family 500K Gates 10476 Cells 572MHz 90nm Technology 1.2V 208-Pin PQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3E XAr
Datasheet
1.XA3S100E-4VQG100I.pdf
(37 pages)
Specifications of XA3S500E-4PQG208Q
Package
208PQFP
Family Name
XA SpartanÂ-3E
Device Logic Units
10476
Device System Gates
500000
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
158
Ram Bits
368640
Number Of Logic Elements/cells
10476
Number Of Labs/clbs
1164
Total Ram Bits
368640
Number Of I /o
158
Number Of Gates
500000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 125°C
Package / Case
208-BFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XA3S500E-4PQG208Q
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XA3S500E-4PQG208Q
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Delay-Locked Loop
Table 26: Recommended Operating Conditions for the DLL
Notes:
1.
2.
3.
4.
Table 27: Switching Characteristics for the DLL
DS635 (v2.0) September 9, 2009
Product Specification
Input Frequency Ranges
F
Input Pulse Requirements
CLKIN_PULSE
Input Clock Jitter Tolerance and Delay Path Variation
CLKIN_CYC_JITT_DLL_LF
CLKIN_CYC_JITT_DLL_HF
CLKIN_PER_JITT_DLL
CLKFB_DELAY_VAR_EXT
Output Frequency Ranges
CLKOUT_FREQ_CLK0
CLKOUT_FREQ_CLK90
CLKOUT_FREQ_2X
CLKOUT_FREQ_DV
Output Clock Jitter
CLKOUT_PER_JITT_0
CLKOUT_PER_JITT_90
CLKOUT_PER_JITT_180
CLKOUT_PER_JITT_270
CLKOUT_PER_JITT_2X
CLKOUT_PER_JITT_DV1
CLKOUT_PER_JITT_DV2
CLKIN
DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See
To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock frequency by two as it enters the DCM. The CLK2X output reproduces the clock frequency provided on the CLKIN input.
CLKIN input jitter beyond these limits might cause the DCM to lose lock.
CLKIN_FREQ_DLL
Symbol
R
Symbol
(2,3,4)
Frequency for the CLK0 and CLK180 outputs
Frequency for the CLK90 and CLK270 outputs
Frequency for the CLK2X and CLK2X180 outputs
Frequency for the CLKDV output
Period jitter at the CLK0 output
Period jitter at the CLK90 output
Period jitter at the CLK180 output
Period jitter at the CLK270 output
Period jitter at the CLK2X and CLK2X180 outputs
Period jitter at the CLKDV output when performing integer
division
Period jitter at the CLKDV output when performing
non-integer division
Frequency of the CLKIN clock input
CLKIN pulse width as a
percentage of the CLKIN
period
Cycle-to-cycle jitter at the
CLKIN input
Period jitter at the CLKIN input
Allowable variation of off-chip feedback delay from the DCM output to
the CLKFB input
Description
(4)
www.xilinx.com
Description
F
F
F
F
CLKIN
CLKIN
CLKIN
CLKIN
< 150 MHz
> 150 MHz
< 150 MHz
> 150 MHz
Table
0.3125
Min
10
5
5
-
-
-
-
-
-
-
-4 Speed Grade
28.
-4 Speed Grade
CLKIN period
CLKIN period
40%
45%
Min
5
(2)
-
-
-
-
±[1% of
±[1% of
+ 150]
+ 200]
±100
±150
±150
±150
±150
Max
240
200
311
160
240
±300
±150
Max
60%
55%
±1
±1
(3)
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
Units
MHz
ps
ps
ns
ns
-
-
25