XA3S500E-4PQG208Q Xilinx Inc, XA3S500E-4PQG208Q Datasheet - Page 21

• Manufacturer Part Number: XA3S500E-4PQG208Q
• Description: FPGA XA Spartan™-3E Family 500K Gates 10476 Cells 572MHz 90nm Technology 1.2V 208-Pin PQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3E XAr

Specifications of XA3S500E-4PQG208Q

• Package: 208PQFP
• Family Name: XA Spartan™-3E
• Device Logic Units: 10476
• Device System Gates: 500000
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 158
• Ram Bits: 368640
• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Total Ram Bits: 368640
• Number Of I /o: 158
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 21: CLB Distributed RAM Switching Characteristics
Table 22: CLB Shift Register Switching Characteristics
DS635 (v2.0) September 9, 2009
Product Specification
Clock-to-Output Times
Setup Times
Hold Times
Clock Pulse Width
Clock-to-Output Times
Setup Times
Hold Times
Clock Pulse Width
T
T
WPH
WPH
T
Symbol
Symbol
T
T
T
AH,
T
SRLDH
SHCKO
SRLDS
T
T
T
T
REG
WS
, T
DS
AS
DH
, T
T
WH
WPL
WPL
R
Time from the active edge at the CLK input to data appearing on the shift
register output
Setup time of data at the BX or BY input before the active transition at the
CLK input of the shift register
Hold time of the BX or BY data input after the active transition at the CLK
input of the shift register
Minimum High or Low pulse width at CLK input
Time from the active edge at the CLK input to data appearing on the
distributed RAM output
Setup time of data at the BX or BY input before the active transition at the
CLK input of the distributed RAM
Setup time of the F/G address inputs before the active transition at the CLK
input of the distributed RAM
Setup time of the write enable input before the active transition at the CLK
input of the distributed RAM
Hold time of the BX, BY data inputs after the active transition at the CLK
input of the distributed RAM
Hold time of the F/G address inputs or the write enable input after the active
transition at the CLK input of the distributed RAM
Minimum High or Low pulse width at CLK input
Description
Description
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0.46
0.52
0.40
0.15
1.01
Min
0.46
0.16
1.01
Min
0
-
-
-4
-4
Max
2.35
Max
4.16
-
-
-
-
-
-
-
-
-
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
21