XA3S500E-4PQG208Q Xilinx Inc, XA3S500E-4PQG208Q Datasheet - Page 32
![FPGA XA Spartan™-3E Family 500K Gates 10476 Cells 572MHz 90nm Technology 1.2V 208-Pin PQFP](/photos/6/71/67100/pq208_sml.jpg)
XA3S500E-4PQG208Q
Manufacturer Part Number
XA3S500E-4PQG208Q
Description
FPGA XA Spartan™-3E Family 500K Gates 10476 Cells 572MHz 90nm Technology 1.2V 208-Pin PQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3E XAr
Datasheet
1.XA3S100E-4VQG100I.pdf
(37 pages)
Specifications of XA3S500E-4PQG208Q
Package
208PQFP
Family Name
XA SpartanÂ-3E
Device Logic Units
10476
Device System Gates
500000
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
158
Ram Bits
368640
Number Of Logic Elements/cells
10476
Number Of Labs/clbs
1164
Total Ram Bits
368640
Number Of I /o
158
Number Of Gates
500000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 125°C
Package / Case
208-BFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XA3S500E-4PQG208Q
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XA3S500E-4PQG208Q
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Slave Parallel Mode Timing
Table 39: Timing for the Slave Parallel Configuration Mode
DS635 (v2.0) September 9, 2009
Product Specification
Notes:
1.
2.
3.
Clock-to-Output Times
T
Setup Times
T
T
T
Hold Times
T
T
T
Clock Timing
T
T
F
SMCKBY
SMDCC
SMCSCC
SMCCW
SMCCD
SMCCCS
SMWCC
CCH
CCL
CCPAR
Symbol
The numbers in this table are based on the operating conditions set forth in
In the Slave Parallel mode, it is necessary to use the BUSY pin when the CCLK frequency exceeds this maximum specification.
Some Xilinx documents refer to Parallel modes as “SelectMAP” modes.
(2)
R
The time from the rising transition on the CCLK pin to a signal transition at the
BUSY pin
The time from the setup of data at the D0-D7 pins to the active edge the CCLK
pin
Setup time on the CSI_B pin before the active edge of the CCLK pin
Setup time on the RDWR_B pin before active edge of the CCLK pin
The time from the active edge of the CCLK pin to the point when data is last
held at the D0-D7 pins
The time from the active edge of the CCLK pin to the point when a logic level
is last held at the CSO_B pin
The time from the active edge of the CCLK pin to the point when a logic level
is last held at the RDWR_B pin
The High pulse width at the CCLK input pin
The Low pulse width at the CCLK input pin
Frequency of the clock
signal at the CCLK input
pin
No bitstream
compression
With bitstream compression
Description
www.xilinx.com
Not using the BUSY pin
Using the BUSY pin
Table
6.
(2)
-4 Speed Grade
11.0
10.0
23.0
Min
1.0
0
0
5
5
0
0
0
-
Max
12.0
50
66
20
-
-
-
-
-
-
-
-
Units
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
32