C8051F066-GQ Silicon Laboratories Inc, C8051F066-GQ Datasheet - Page 281
C8051F066-GQ
Manufacturer Part Number
C8051F066-GQ
Description
MCU 8-Bit C8051F06x 8051 CISC 32KB Flash 3.3V 100-Pin TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F06xr
Specifications of C8051F066-GQ
Package
100TQFP
Device Core
8051
Family Name
C8051F06x
Maximum Speed
25 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
8 Bit
Number Of Programmable I/os
59
Interface Type
I2C/SMBus/SPI/UART
On-chip Adc
2-chx16-bit
Number Of Timers
5
Ram Size
4.25 KB
Program Memory Size
32 KB
Program Memory Type
Flash
Operating Temperature
-40 to 85 °C
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
59
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
336-1221
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Part Number:
C8051F066-GQ
Manufacturer:
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23.3. Multiprocessor Communications
9-Bit UART mode supports multiprocessor communication between a master processor and one or more
slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or
more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte
in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0.
Setting the MCE1 bit (SCON.5) of a slave processor configures its UART such that when a stop bit is
received, the UART will generate an interrupt only if the ninth bit is logic one (RB81 = 1) signifying an
address byte has been received. In the UART interrupt handler, software should compare the received
address with the slave's own assigned 8-bit address. If the addresses match, the slave should clear its
MCE1 bit to enable interrupts on the reception of the following data byte(s). Slaves that weren't addressed
leave their MCE1 bits set and do not generate interrupts on the reception of the following data bytes,
thereby ignoring the data. Once the entire message is received, the addressed slave should reset its
MCE1 bit to ignore all transmissions until it receives the next address byte.
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple
slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master
processor can be configured to receive all transmissions or a protocol can be implemented such that the
master/slave role is temporarily reversed to enable half-duplex transmission between the original master
and slave(s).
RX
Master
Device
Figure 23.6. UART Multi-Processor Mode Interconnect Diagram
TX
RX
Device
Slave
TX
Rev. 1.2
RX
Device
Slave
C8051F060/1/2/3/4/5/6/7
TX
RX
Device
Slave
TX
+5V
281
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