C8051F066-GQ Silicon Laboratories Inc, C8051F066-GQ Datasheet - Page 224

• Manufacturer Part Number: C8051F066-GQ
• Description: MCU 8-Bit C8051F06x 8051 CISC 32KB Flash 3.3V 100-Pin TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F06xr

Specifications of C8051F066-GQ

• Package: 100TQFP
• Device Core: 8051
• Family Name: C8051F06x
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 59
• Interface Type: I2C/SMBus/SPI/UART
• On-chip Adc: 2-chx16-bit
• Number Of Timers: 5
• Ram Size: 4.25 KB
• Program Memory Size: 32 KB
• Program Memory Type: Flash
• Operating Temperature: -40 to 85 °C
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 59
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 336-1221

C8051F060/1/2/3/4/5/6/7
224
Bits7-0:
Note:
Bits7-0:
P7.7
R/W
R/W
Bit7
Bit7
P7.[7:0]: Port7 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (open, if corresponding P7MDOUT bit = 0). See Figure 18.26.
Read - Returns states of I/O pins.
0: P7.n pin is logic low.
1: P7.n pin is logic high.
P7.[7:0] can be driven by the External Data Memory Interface (as AD[7:0] in Multiplexed
mode, or as D[7:0] in Non-multiplexed mode). See
face and On-Chip XRAM” on page 187
Interface.
P7MDOUT.[7:0]: Port7 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
P7.6
R/W
R/W
Bit6
Bit6
Figure 18.26. P7MDOUT: Port7 Output Mode Register
P7.5
R/W
R/W
Bit5
Bit5
Figure 18.25. P7: Port7 Data Register
P7.4
R/W
R/W
Bit4
Bit4
Rev. 1.2
P7.3
R/W
R/W
Bit3
Bit3
for more information about the External Memory
P7.2
R/W
R/W
Bit2
Bit2
Section “17. External Data Memory Inter-
P7.1
R/W
R/W
Bit1
Bit1
SFR Address:
SFR Address:
SFR Page:
SFR Page:
P7.0
R/W
R/W
Bit0
Bit0
0xF8
F
0x9F
F
Addressable
Reset Value
Reset Value
00000000
11111111
Bit