C8051F066-GQ Silicon Laboratories Inc, C8051F066-GQ Datasheet - Page 123
C8051F066-GQ
Manufacturer Part Number
C8051F066-GQ
Description
MCU 8-Bit C8051F06x 8051 CISC 32KB Flash 3.3V 100-Pin TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F06xr
Specifications of C8051F066-GQ
Package
100TQFP
Device Core
8051
Family Name
C8051F06x
Maximum Speed
25 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
8 Bit
Number Of Programmable I/os
59
Interface Type
I2C/SMBus/SPI/UART
On-chip Adc
2-chx16-bit
Number Of Timers
5
Ram Size
4.25 KB
Program Memory Size
32 KB
Program Memory Type
Flash
Operating Temperature
-40 to 85 °C
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
59
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
336-1221
Available stocks
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Price
Company:
Part Number:
C8051F066-GQ
Manufacturer:
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Quantity:
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13.
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The MCU family has a superset of all the peripherals included with a standard 8051. Included are
five 16-bit counter/timers (see description in
22
(see
includes on-chip debug hardware (see description in
analog and digital subsystems providing a complete data acquisition or control-system solution in a single
integrated circuit.
-
-
-
-
-
and
Fully Compatible with MCS-51 Instruction Set
25 MIPS Peak Throughput with 25 MHz Clock
0 to 25 MHz Clock Frequency
256 Bytes of Internal RAM
59/24 General-Purpose I/O Pins
Section
Section
CIP-51 Microcontroller
13.2.6), and 59/24 General-Purpose I/O Pins (see description in
23), 256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space
Section
Rev. 1.2
24), two full-duplex UARTs (see description in
Section
-
-
-
-
-
C8051F060/1/2/3/4/5/6/7
Extended Interrupt Handler
Reset Input
Power Management Modes
On-chip Debug Logic
Program and Data Memory Security
26), and interfaces directly with the MCU’s
Section
18). The CIP-51 also
Section
123
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