72V2103L15PFG Integrated Device Technology (Idt), 72V2103L15PFG Datasheet - Page 9

• Manufacturer Part Number: 72V2103L15PFG
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 128K x 18/256K x 9 80-Pin TQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72V2103L15PFG

• Package: 80TQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 2.25 Mb
• Organization: 128Kx18|256Kx9
• Data Bus Width: 18|9 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: 0 to 70 °C

NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range product for the 7-5ns and 10ns are available as a standard device. All other speed grades are available by special order.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
5. TQFP package only: for speed grades 7-5ns, 10ns and 15ns the minimum for t
AC ELECTRICAL CHARACTERISTICS
(Commercial: V
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
Symbol
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
S
A
CLK
CLKH
DS
DH
ENH
LDS
LDH
RS
RSR
CLKL
ENS
RSS
RSF
RTS
OLZ
OE
OHZ
WFF
REF
PAFA
PAFS
PAEA
PAES
HF
SKEW1
SKEW2
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock High Time
Clock Low Time
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Load Setup Time
Load Hold Time
Reset Pulse Width
Reset Setup Time
Reset Recovery Time
Reset to Flag and Output Time
Retransmit Setup Time
Output Enable to Output in Low Z
Output Enable to Output Valid
Output Enable to Output in High Z
Write Clock to FF or IR
Read Clock to EF or OR
Clock to Asynchronous Programmable Almost-Full Flag
Write Clock to Synchronous Programmable Almost-Full Flag
Clock to Asynchronous Programmable Almost-Empty Flag
Read Clock to Synchronous Programmable Almost-Empty Flag
Clock to HF
Skew time between RCLK and WCLK for EF/OR and FF/IR
Skew time between RCLK and WCLK for PAE and PAF
CC
= 3.3V ± 0.15V, T
(5)
(3)
Parameter
A
(5)
= 0°C to +70°C; Industrial: V
(4)
(4,5)
TM
NARROW BUS FIFO
CC
= 3.3V ± 0.15V, T
(1)
A
IDT72V2103L6
IDT72V2113L6
Min.
BGA & TQFP
, t
Commercial
TM
2.7
2.7
0.5
0.5
0.5
—
10
15
10
—
—
—
—
—
—
—
—
1
6
2
2
3
3
0
1
1
4
5
OE
9
NARROW BUS FIFO
, and t
Max.
166
OHZ
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
10
10
10
—
—
4
4
4
4
4
4
4
is 2ns.
A
IDT72V2103L7-5
IDT72V2113L7-5
Com’l & Ind’l
= -40°C to +85°C; JEDEC JESD8-A compliant)
BGA & TQFP
Min.
1
7.5
3.5
3.5
2.5
0.5
2.5
0.5
3.5
0.5
3.5
1
1
—
10
15
10
—
—
—
—
—
—
—
—
0
5
7
(5)
(5)
(5)
133.3
Max.
12.5
12.5
12.5
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
—
—
5
6
6
5
5
5
5
(2)
IDT72V2103L10
IDT72V2113L10
Com’l & Ind’l
Min.
1
4.5
4.5
3.5
0.5
3.5
0.5
3.5
0.5
3.5
1
1
10
10
15
10
—
—
—
—
—
—
—
—
10
—
TQFP Only
0
7
(5)
(5)
(5)
COMMERCIAL AND INDUSTRIAL
Max.
100
6.5
6.5
6.5
6.5
6.5
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
16
16
16
—
—
6
6
(2)
TEMPERATURE RANGES
IDT72V2103L15
IDT72V2113L15
Min.
1
1
1
—
15
15
15
15
—
—
—
—
—
—
—
—
14
Commercial
TQFP Only
6
6
4
1
4
1
4
1
4
0
9
(5)
(5)
(5)
JUNE 1, 2010
66.7
Max.
10
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
10
10
20
10
20
10
20
—
—
8
8
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns