72V2103L15PFG Integrated Device Technology (Idt), 72V2103L15PFG Datasheet - Page 33

• Manufacturer Part Number: 72V2103L15PFG
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 128K x 18/256K x 9 80-Pin TQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72V2103L15PFG

• Package: 80TQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 2.25 Mb
• Organization: 128Kx18|256Kx9
• Data Bus Width: 18|9 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: 0 to 70 °C

NOTE:
1. This diagram is based on programming the IDT72V2103/72V2113 x18 bus width. Add one extra cycle to both the PAE offset and PAF offset for x9 bus width.
NOTES:
1. OE = LOW.
2. This diagram is based on programming the IDT72V2103/72V2113 x18 bus width. Add one extra cycle to both the PAE offset and PAF offset for x9 bus width.
NOTES:
1. m = PAF offset .
2. D = maximum FIFO depth.
3. t
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
D
Q
WCLK
RCLK
WEN
In IDT Standard mode: if x18 Input or x18 Output bus Width is selected, D = 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113. If both x9 Input and x9 Output bus Widths
are selected, D = 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113.
In FWFT mode: if x18 Input or x18 Output bus Width is selected, D = 131,073 for the IDT72V2103 and 262,145 for the IDT72V2113. If both x9 Input and x9 Output bus Widths
are selected, D = 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113.
rising edge of RCLK and the rising edge of WCLK is less than t
0
REN
WCLK
0
PAF
SKEW2
RCLK
- D
WEN
- Q
REN
LD
16
LD
16
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t
DATA IN OUTPUT
t
CLKH
REGISTER
Figure 18. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
Figure 16. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
t
ENS
LDS
Figure 17. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
ENS
t
CLKL
t
CLKH
D-(m+1) words in FIFO
PAE OFFSET (LSB)
t
t
CLK
ENH
t
CLKH
t
t
A
t
LDH
t
t
ENS
t
ENH
LDS
t
CLKL
DS
t
CLK
1
t
( 2)
CLKL
PAE OFFSET
SKEW2
TM
(LSB)
t
t
t
ENH
LDH
DH
PAE OFFSET (MSB)
NARROW BUS FIFO
, then the PAF deassertion time may be delayed one extra WCLK cycle.
t
A
2
TM
t
DS
t
PAFS
33
NARROW BUS FIFO
PAE OFFSET
t
ENS
(MSB)
t
SKEW2
t
PAF OFFSET (LSB)
DH
(3)
t
A
t
t
DS
D - m words in FIFO
ENH
1
PAF OFFSET
(LSB)
PAF OFFSET (MSB)
t
COMMERCIAL AND INDUSTRIAL
DH
(2)
t
A
t
t
LDH
ENH
2
TEMPERATURE RANGES
t
PAFS
t
DS
PAFS
). If the time between the
PAF OFFSET
JUNE 1, 2010
(MSB)
D-(m+1) words
in FIFO
6119 drw19
6119 drw21
6119 drw20
t
t
t
ENH
DH
LDH
( 2)