72V2103L15PFG Integrated Device Technology (Idt), 72V2103L15PFG Datasheet - Page 16

• Manufacturer Part Number: 72V2103L15PFG
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 128K x 18/256K x 9 80-Pin TQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72V2103L15PFG

• Package: 80TQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 2.25 Mb
• Organization: 128Kx18|256Kx9
• Data Bus Width: 18|9 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: 0 to 70 °C

NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
LD
0
0
0
X
1
1
1
WEN
1
1
0
X
1
0
1
REN
0
1
1
1
X
0
1
SEN
1
1
0
1
X
X
X
WCLK
X
X
X
X
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
RCLK
X
X
X
X
X
Serial shift into registers:
36 bits for the IDT72V2103
38 bits for the IDT72V2113
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
TM
NARROW BUS FIFO
x9 to x9 Mode
TM
NARROW BUS FIFO
16
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Read Memory
No Operation
Write Memory
No Operation
IDT72V2103
IDT72V2113
Serial shift into registers:
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
34 bits for the IDT72V2103
36 bits for the IDT72V2113
COMMERCIAL AND INDUSTRIAL
All Other Modes
TEMPERATURE RANGES
JUNE 1, 2010
6119 drw06b