MT48LC4M32LFF5-8 IT:G TR Micron Technology Inc, MT48LC4M32LFF5-8 IT:G TR Datasheet - Page 71
![DRAM Chip Mobile SDRAM 128M-Bit 4Mx32 3.3V 90-Pin VFBGA T/R](/photos/7/23/72313/mfg557-90-vfbga_sml.jpg)
MT48LC4M32LFF5-8 IT:G TR
Manufacturer Part Number
MT48LC4M32LFF5-8 IT:G TR
Description
DRAM Chip Mobile SDRAM 128M-Bit 4Mx32 3.3V 90-Pin VFBGA T/R
Manufacturer
Micron Technology Inc
Type
Mobile SDRAMr
Datasheet
1.MT48LC8M16LFB4-75MG_TR.pdf
(80 pages)
Specifications of MT48LC4M32LFF5-8 IT:G TR
Density
128 Mb
Maximum Clock Rate
125 MHz
Package
90VFBGA
Address Bus Width
14 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
19|8|7 ns
Operating Temperature
-40 to 85 °C
Format - Memory
RAM
Memory Type
Mobile SDRAM
Memory Size
128M (4Mx32)
Speed
125MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
90-VFBGA
Organization
4Mx32
Address Bus
14b
Access Time (max)
19/8/7ns
Operating Supply Voltage (typ)
3.3V
Package Type
VFBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
115mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Figure 50:
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
DQMU, DQML
COMMAND
A0–A9, A11
BA0, BA1
CKE
CLK
A10
DQ
t CKS
t CMS
t AS
t AS
t AS
ACTIVE
T0
ROW
ROW
Write – Without Auto Precharge
BANK
t CKH
t CMH
t AH
t AH
t AH
t CK
Notes:
t RCD
t RAS
t RC
T1
NOP
1. For this example, BL = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 15ns is required between <D
3. x16: A9 and A11 = “Don’t Care.”
DISABLE AUTO PRECHARGE
quency.
x32: A8, A9, and A11 = “Don’t Care.”
See Table 17 on page 53.
t CMS
t CL
t DS
COLUMN m 3
WRITE
T2
BANK
D
IN
t CMH
t CH
t DH
m
t DS
D
IN
T3
NOP
m + 1
t DH
t DS
D
T4
IN
NOP
m + 2
t DH
71
IN
m + 3> and the PRECHARGE command regardless of fre-
t DS
D
IN
T5
NOP
m + 3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t DH
t WR
128Mb: x16, x32 Mobile SDRAM
NOP
T6
2
SINGLE BANK
PRECHARGE
ALL BANKS
BANK
T7
©2001 Micron Technology, Inc. All rights reserved.
UNDEFINED
Timing Diagrams
t RP
NOP
T8
ACTIVE
ROW
BANK
ROW
T9
DON’T CARE