MT48LC4M32LFF5-8 IT:G TR Micron Technology Inc, MT48LC4M32LFF5-8 IT:G TR Datasheet - Page 69
![DRAM Chip Mobile SDRAM 128M-Bit 4Mx32 3.3V 90-Pin VFBGA T/R](/photos/7/23/72313/mfg557-90-vfbga_sml.jpg)
MT48LC4M32LFF5-8 IT:G TR
Manufacturer Part Number
MT48LC4M32LFF5-8 IT:G TR
Description
DRAM Chip Mobile SDRAM 128M-Bit 4Mx32 3.3V 90-Pin VFBGA T/R
Manufacturer
Micron Technology Inc
Type
Mobile SDRAMr
Datasheet
1.MT48LC8M16LFB4-75MG_TR.pdf
(80 pages)
Specifications of MT48LC4M32LFF5-8 IT:G TR
Density
128 Mb
Maximum Clock Rate
125 MHz
Package
90VFBGA
Address Bus Width
14 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
19|8|7 ns
Operating Temperature
-40 to 85 °C
Format - Memory
RAM
Memory Type
Mobile SDRAM
Memory Size
128M (4Mx32)
Speed
125MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
90-VFBGA
Organization
4Mx32
Address Bus
14b
Access Time (max)
19/8/7ns
Operating Supply Voltage (typ)
3.3V
Package Type
VFBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
115mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Figure 48:
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
DQMU, DQML
A0–A9, A11
COMMAND
BA0, BA1
CKE
A10
CLK
DQ
t CKS
t CMS
t AS
t AS
t AS
ACTIVE
BANK
T0
ROW
ROW
Read – Full-Page Burst
t CKH
t CMH
t AH
t AH
t AH
t CK
t RCD
Notes:
T1
NOP
1. For this example, CL = 2.
2. x16: A9 and A11 = “Don’t Care.”
3. Page left open; no
x32: A8, A9, and A11 = “Don’t Care.”
See Table 17 on page 53.
t CMS
t CL
COLUMN m 2
T2
BANK
READ
t CMH
t CH
CAS Latency
T3
NOP
t LZ
t AC
t
RP.
T4
D
NOP
OUT
t OH
512 (x16) locations within same row
m
69
t AC
Full-page burst does not self-terminate.
Can use BURST TERMINATE command.
D
T5
OUT
NOP
t OH
m+1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Full page completed
t AC
D
T6
OUT
128Mb: x16, x32 Mobile SDRAM
NOP
t OH
t AC
m+2
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Tn + 1
D
NOP
OUT
t OH
m-1
t AC
©2001 Micron Technology, Inc. All rights reserved.
BURST TERM
Tn + 2
3
Timing Diagrams
D
OUT
UNDEFINED
t OH
m
t AC
Tn + 3
D
OUT
NOP
t OH
m+1
t HZ
DON’T CARE
Tn + 4
NOP