MT48LC4M32LFF5-8 IT:G TR Micron Technology Inc, MT48LC4M32LFF5-8 IT:G TR Datasheet - Page 62
![DRAM Chip Mobile SDRAM 128M-Bit 4Mx32 3.3V 90-Pin VFBGA T/R](/photos/7/23/72313/mfg557-90-vfbga_sml.jpg)
MT48LC4M32LFF5-8 IT:G TR
Manufacturer Part Number
MT48LC4M32LFF5-8 IT:G TR
Description
DRAM Chip Mobile SDRAM 128M-Bit 4Mx32 3.3V 90-Pin VFBGA T/R
Manufacturer
Micron Technology Inc
Type
Mobile SDRAMr
Datasheet
1.MT48LC8M16LFB4-75MG_TR.pdf
(80 pages)
Specifications of MT48LC4M32LFF5-8 IT:G TR
Density
128 Mb
Maximum Clock Rate
125 MHz
Package
90VFBGA
Address Bus Width
14 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
19|8|7 ns
Operating Temperature
-40 to 85 °C
Format - Memory
RAM
Memory Type
Mobile SDRAM
Memory Size
128M (4Mx32)
Speed
125MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
90-VFBGA
Organization
4Mx32
Address Bus
14b
Access Time (max)
19/8/7ns
Operating Supply Voltage (typ)
3.3V
Package Type
VFBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
115mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Figure 41:
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
DQMU, DQML
Auto Refresh Mode
COMMAND
A0–A9, A11
BA0, BA1
Notes:
CLK
CKE
A10
DQ
Precharge all
High-Z
t CKS
active banks
t CMS
t AS
SINGLE BANK
ALL BANKS
PRECHARGE
BANK(S)
1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back commands are not
2.
T0
t AH
t CKH
t CMH
required. See Table 17 on page 53.
t
commands must be applied on each positive clock edge during
t CK
RFC must not be interrupted by any executable command; COMMAND INHIBIT or NOP
t RP
T1
NOP
T2
REFRESH
AUTO
t CH
t RFC
62
1, 2
NOP
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
t CL
Tn + 1
REFRESH
AUTO
128Mb: x16, x32 Mobile SDRAM
t RFC
NOP
1, 2
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t
©2001 Micron Technology, Inc. All rights reserved.
RFC.
To + 1
ACTIVE
ROW
ROW
BANK
Timing Diagrams
DON’T CARE