MT48LC4M32B2P-6 IT:G Micron Technology Inc, MT48LC4M32B2P-6 IT:G Datasheet - Page 16
MT48LC4M32B2P-6 IT:G
Manufacturer Part Number
MT48LC4M32B2P-6 IT:G
Description
DRAM Chip SDRAM 128M-Bit 4Mx32 3.3V 86-Pin TSOP-II Tray
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC4M32B2P-7G_TR.pdf
(67 pages)
Specifications of MT48LC4M32B2P-6 IT:G
Package
86TSOP-II
Density
128 Mb
Address Bus Width
14 Bit
Operating Supply Voltage
3.3 V
Maximum Clock Rate
166 MHz
Maximum Random Access Time
17|7.5|5.5 ns
Operating Temperature
-40 to 85 °C
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Operating Mode
Write Burst Mode
Table 7:
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. L 1/09 EN
CAS Latency
The normal operating mode is selected by setting M7 and M8 to zero; the other combi-
nations of values for M7 and M8 are reserved for future use and/or test modes. The
programmed BL applies to both read and write bursts.
Test modes and reserved states should not be used because unknown operation or
incompatibility with future versions may result.
When M9 = 0, BL programmed via M0–M2 applies to both read and write bursts; when
M9 = 1, the programmed BL applies to read bursts, but write accesses are single-location
(nonburst) accesses.
Speed
-6
-7
16
CL = 1
≤ 50
≤ 50
Allowable Operating Frequency (MHz)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CL = 2
≤ 100
≤ 100
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
Register Definition
CL = 3
≤ 166
≤ 143
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