ATF-541M4-BLK Avago Technologies US Inc., ATF-541M4-BLK Datasheet - Page 12

• Manufacturer Part Number: ATF-541M4-BLK
• Description: IC ENHANCED MOD SUDIOMORPHIC HEM
• Manufacturer: Avago Technologies US Inc.

Specifications of ATF-541M4-BLK

• Gain: 17.5dB
• Package / Case: 4-MiniPak (1412)
• Current Rating: 120mA
• Power - Output: 21.4dBm
• Frequency: 2GHz
• Transistor Type: pHEMT FET
• Noise Figure: 0.5dB
• Current - Test: 60mA
• Voltage - Test: 3V
• Drain Source Voltage Vds: 3V
• Continuous Drain Current Id: 120mA
• Power Dissipation Pd: 360mW
• Noise Figure Typ: 0.5dB
• Rf Transistor Case: MiniPak
• No. Of Pins: 4
• Frequency Max: 10GHz
• Drain Current Idss Max: 60mA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q2380948

12
ATF-541M4 Applications Infor-
mation
Introduction
Avago Technologies’s ATF­‑541M4 is a
low noise enhancement mode PHEMT
designed for use in low cost commer‑
cial applications in the VHF­ through 6
GHz frequency range. As opposed to a
typical depletion mode PHEMT where
the gate must be made negative with
respect to the source for proper opera‑
tion, an enhancement mode PHEMT
requires that the gate be made more
positive than the source for normal
operation. Therefore a negative power
supply voltage is not required for an
enhancement mode device. Biasing an
enhancement mode PHEMT is much
like biasing the typical bipolar junc‑
tion transistor. Instead of a 0.7V base
to emitter voltage, the ATF­‑541M4
enhancement mode PHEMT requires a
nominal 0.58V potential between the
gate and source for a nominal drain
current of 60 mA.
Matching Networks
The techniques for impedance match‑
ing an enhancement mode device are
very similar to those for matching a
depletion mode device. The only dif‑
ference is in the method of supplying
gate bias. S and Noise Parameters for
various bias conditions are listed in this
data sheet. The circuit shown in F­igure
1 shows a typical LNA circuit normally
used for 900 and 1900 MHz applica‑
tions. (Consult the Avago Technologies
web site for application notes covering
specific designs and applications). High
pass impedance matching networks
consisting of L1/C1 and L4/C4 provide
the appropriate match for noise fig‑
ure, gain, S11 and S22. The high pass
structure also provides low frequency
gain reduction which can be beneficial
from the standpoint of improving out‑
of‑band rejection.
Capacitors C2 and C5 provide a low
impedance in‑band RF­ bypass for
the matching networks. Resistors R3
and R4 provide a very important low
frequency termination for the device.
The resistive termination improves
low frequency stability. Capacitors
C3 and C6 provide the RF­ bypass
for resistors R3 and R4. Their value
should be chosen carefully as C3 and
C6 also provide a termination for low
frequency mixing products. These
mixing products are as a result of two
or more in‑band signals mixing and
producing third order in‑band distor‑
tion products. The low frequency or
difference mixing products are termi‑
nated by C3 and C6. F­or best suppres‑
sion of third order distortion products
based on the CDMA 1.25 MHz signal
spacing, C3 and C6 should be 0.1 uF­
in value. Smaller values of capacitance
will not suppress the generation of
the 1.25 MHz difference signal and
as a result will show up as poorer two
tone IP3 results.
Figure 1. Typical ATF-541M4 LNA with Passive Biasing.
Bias Networks
One of the major advantages of the
enhancement mode technology is
that it allows the designer to be able
to dc ground the source leads and
then merely apply a positive voltage
on the gate to set the desired amount
of quiescent drain current Id.
Whereas a depletion mode PHEMT
pulls maximum drain current when
V
PHEMT pulls only a small amount of
INPUT
gs
= 0 V, an enhancement mode
Zo
R1
R5
R4
C1
L1
C3
C2
R2
Q1
L2
L3
Vdd
L4
R3
C5
C6
C4
Zo
OUTPUT
leakage current when V
when V
device threshold voltage, will drain
current start to flow. At a V
a nominal V
rent I
The data sheet suggests a minimum
and maximum V
desired amount of drain current will
be achieved. It is also important to
note that if the gate terminal is left
open circuited, the device will pull
some amount of drain current due
to leakage current creating a voltage
differential between the gate and
source terminals.
Passive Biasing
Passive biasing of the ATF­‑541M4 is
accomplished by the use of a volt‑
age divider consisting of R1 and R2
connected to the gate of the device.
The voltage for the divider is derived
from the drain voltage. This provides a
form of voltage feedback (through the
use of R3) to help keep drain current
constant. Resistor R5 (approximately
10KΩ) is added to limit the gate cur‑
rent of enhancement mode devices
such as the ATF­‑541M4. This is espe‑
cially important when the device is
driven to P1dB or Psat.
Resistor R3 is calculated based on
desired V
supply voltage.
R3 = V
V
V
age.
I
I
the R1/R2 resistor voltage divider
network.
ds
BB
DD
ds
is the desired drain current.
is the current flowing through
is the device drain to source volt‑
is the power supply voltage.
d
I
ds
DD
will be approximately 60 mA.
gs
+ I
– V
ds
is increased above V
BB
, I
gs
ds
ds
of 0.58V, the drain cur‑
and available power
(1)
gs
over which the
gs
ds
= 0V. Only
of 3V and
to
, the