ATF-55143-BLKG Avago Technologies US Inc., ATF-55143-BLKG Datasheet - Page 15

• Manufacturer Part Number: ATF-55143-BLKG
• Description: IC PHEMT 2GHZ 2.7V 10MA SOT-343
• Manufacturer: Avago Technologies US Inc.

Specifications of ATF-55143-BLKG

• Package / Case: SC-70-4, SC-82-4, SOT-323-4, SOT-343
• Transistor Type: pHEMT FET
• Frequency: 2GHz
• Gain: 17.7dB
• Voltage - Rated: 5V
• Current Rating: 100mA
• Noise Figure: 0.6dB
• Current - Test: 10mA
• Voltage - Test: 2.7V
• Power - Output: 14.4dBm
• Configuration: Single Dual Source
• Transistor Polarity: N-Channel
• Power Dissipation: 270 mW
• Drain Source Voltage Vds: 5 V
• Gate-source Breakdown Voltage: - 5 V to 1 V
• Continuous Drain Current: 100 mA
• Maximum Operating Temperature: + 150 C
• Maximum Drain Gate Voltage: - 5 V to 1 V
• Minimum Operating Temperature: - 65 C
• Mounting Style: SMD/SMT
• Continuous Drain Current Id: 100mA
• Power Dissipation Pd: 270mW
• Noise Figure Typ: 0.6dB
• Rf Transistor Case: SC-70
• No. Of Pins: 4
• Frequency Max: 6GHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 516-1869; ATF-55143-BLKG

The values of resistors R1 and R2 are calculated with the
following formulas
R1 =
R2 =
Example Circuit
V
V
I
V
Choose I
leakage current. I
0.5 mA for this example. Using equations (1), (2), and (3)
the resistors are calculated as follows
R1 = 940Ω
R2 = 4460Ω
R3 = 28.6Ω
Active Biasing
Active biasing provides a means of keeping the quies‑
cent bias point constant over temperature and constant
over lot to lot variations in device dc performance. The
advantage of the active biasing of an enhancement
mode PHEMT versus a depletion mode PHEMT is that a
negative power source is not required. The techniques
of active biasing an enhancement mode device are very
similar to those used to bias a bipolar junction transis‑
tor.
INPUT
Figure 34. Typical ATF-55143 LNA with Active Biasing.
An active bias scheme is shown in Figure 34. R1 and R2
provide a constant voltage source at the base of a PNP
transistor at Q2. The constant voltage at the base of Q2
is raised by 0.7 volts at the emitter. The constant emitter
voltage plus the regulated V
resistor R3. Constant voltage across R3 provides a con‑
stant current supply for the drain current. Resistors R1
and R2 are used to set the desired Vds. The combined
15
ds
ds
DD
gs
= 10 mA
= 2.7V
= 0.47 V
= 3V
Zo
V
(V
I
R7
BB
gs
R5
R6
ds
C1
L1
BB
p
– V
V
(2)
R1
gs
to be at least 10X the normal expected gate
C3
C2
gs
) R1
Q1
L2
C7
Q2
p
BB
(3)
L3
was conservatively chosen to be
R2
L4
C5
R4
C6
C4
DD
R3
Zo
supply are present across
OUTPUT
Vdd
series value of these resistors also sets the amount of
extra current consumed by the bias network. The equa‑
tions that describe the circuit’s operation are as follows.
V
R3 =
V
V
V
Rearranging equation (4) provides the following for‑
mula
R2 =
and rearranging equation (5) provides the following
formula
R1 =
Example Circuit
V
V
I
R4 = 10Ω
V
Equation (1) calculates the required voltage at the emit‑
ter of the PNP transistor based on desired V
through resistor R4 to be 2.8V. Equation (2) calculates
the value of resistor R3 which determines the drain cur‑
rent I
the voltage required at the junction of resistors R1 and
R2. This voltage plus the step‑up of the base emitter
junction determines the regulated V
(5) are solved simultaneously to determine the value
of resistors R1 and R2. In the example R1=4200Ω and
R2 =1800Ω. R7 is chosen to be 1kΩ. This resistor keeps
a small amount of current flowing through Q2 to help
maintain bias stability. R6 is chosen to be 10kΩ. This
value of resistance is necessary to limit Q1 gate current
in the presence of high RF drive levels (especially when
Q1 is driven to the P
provides a low frequency bypass to keep noise from Q2
effecting the operation of Q1. C7 is typically 0.1 µF.
ds
ds
E
B
B
DD
DD
BE
= 10 mA
= V
= V
=
= 2.7V
= 0.7 V
= 3V
= I
ds
V
R1 + R2
I
ds
E
R
BB
BB
. In the example R3 = 20Ω. Equation (3) calculates
DD
– V
1
+ (I
R1
(
(R1 + R2)
(V
I
– V
ds
1 + V
BE
ds
DD
V
E
•
B
– V
V
p
R4)
V
p
I
DD
BB
DD
DD
B
V
= 0.5 mA
)
– V
B
(1)
(3)
(5)
B
(4A)
(2)
(4)
p
)
1dB
9
gain compression point). C7
(5A)
ds
. Equations (4) and
ds
and I
ds